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ADC12D1620LGMPR Datasheet(PDF) 6 Page - Texas Instruments |
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ADC12D1620LGMPR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 82 page  VA GND GND VA 50k VA AGND VA AGND 50k Control from VCMO VCMO 100 6 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Product Folder Links: ADC12D1620QML-SP Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions: Analog Front-End and Clock Pins (continued) PIN TYPE DESCRIPTION EQUIVALENT CIRCUIT NAME NO. VinI+, VinI– VinQ+, VinQ– H1/J1 N1/M1 I Differential signal I and Q inputs. In the non-dual edge sampling (non-DES) mode, each I and Q input is sampled and converted by its respective channel with each positive transition of the CLK input. In non-ECM (non-extended control mode) and DES mode, both channels sample the I input. In Extended Control mode (ECM), the Q input may optionally be selected for conversion in DES mode by the DEQ Bit of the Configuration Register (Addr: 0h; Bit: 6). Each I- and Q-channel input has an internal common mode bias that is disabled when DC- coupled mode is selected. Both inputs must be either AC- or DC-coupled. The coupling mode is selected by the VCMO pin. In non-ECM, the full-scale range of these inputs is determined by the FSR pin; both I and Q channels have the same full-scale input range. In ECM, the full-scale input range of the I- and Q-channel inputs may be independently set with the I- and Q-channel Full-Scale Range Adjust Registers (Addr: 3h and Addr: Bh, respectively). The high and low full-scale input range setting in non-ECM corresponds to the mid and minimum full-scale input range in ECM. The input offset may also be adjusted in ECM with the I- and Q-channel Offset Adjust Registers (Addr: 2h and Addr: Ah, respectively). CONTROL AND STATUS PINS CAL D6 I Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high for a minimum of tCAL_H after having held it low for a minimum of tCAL_L. This pin is active in both ECM and non-ECM. In ECM, this pin is logically OR'd with the CAL Bit of the Configuration Register (Addr: 0h, Bit 15). Therefore, both the pin and bit must be set low and then either can be set high to execute an on-command calibration. TI recommends holding the CAL pin high during normal usage to reduce the chance that an SEU causes a calibration cycle. CalRun B5 O Calibration running indication. This output is logic- high while the calibration sequence is executing; otherwise, this output is logic-low. |
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