i960 CACF INTERFACE

The following pins are functionally equivalent to those on

the i960 CACF from which their names are taken Like

named pins on the i960 CACF and the NSBMC960 are to

be wired together All 3-State outputs are to be weakly

sufficient

Pin

Description

A2–31

Address Bus (Input)

This system bus is a word address which determines the location at which an access is

required

ADS

Address Strobe (Input Active Low)

Indicates that a new access cycle is being started

D

C

Data

Code (Input)

Signals whether an access is for data or instructions

BLAST

Burst Last (Input Active Low)

Indicates that the last cycle of a burst is in progress

DEN

Data Enable (Input Active Low)

This input is monitored by the Bus Watch Timer to detect a bus access not

returning READY

BTERM

Burst Terminate (Output 3-State Active Low)

This output is used to request termination of a burst in progress

Used to disable burst writes

READY

Data Ready (Output 3-State Active Low)

The READY output is used to signal that data on the processor bus is

valid for Read or that data has been accepted for Write

RESET

Reset (Input Active Low)

Assertion of this input sets the NSBMC960 to its initial state Following initialization the

NSBMC960 must be configured before any memory access is possible

BE0–3

Byte Enable (Input Active Low)

These inputs are used to determine which byte(s) within the addressed word are to

be accessed

W

R

WRITE

READ (Input)

This input indicates the direction which data is to be transferred tofrom on the data bus

SUP

Supervisor (Input Active Low)

Indicates that the processor is operating in supervisor mode Required for access to

configuration registers

PCLK

System Clock (Input)

Processor output clock required to operate and synchronize NSBMC960 internal functions

BERR

Bus Error (Output Active Low)

When enabled this signal is generated by the Bus Watch Circuit to prevent

processor lock-up on access to a region that is not responding

INT

Interrupt (Output 12 mA Active Low)

This signal is assented when the 24-bit counter reaches terminal count and

interrupt out is enabled May be programmed for pulse or handshake operation

ID0–2

Chip ID (Input)

These inputs select the address offset of the NSBMC960 configuration registers Each NSBMC960 in

a system must have a unique address for proper operation

4