SiC620R, SiC620AR

www.vishay.com

Vishay Siliconix

S14-2189, Rev. A 03-Nov-14

2

Document Number: 63589

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

PINOUT CONFIGURATION

Fig. 2 - SiC620R and SiC620AR Pin Configuration

PIN CONFIGURATION

PIN NUMBER

NAME

FUNCTION

1PWM

PWM control input

2

ZCD_EN#

ZCD control. Active low

Supply voltage for internal logic circuitry

4, 32

Analog ground for the driver IC

5

BOOT

High-side driver bootstrap voltage

6

GH

High-side gate signal

7

PHASE

Return path of high-side gate driver

8 to 11, 34

Power stage input voltage. Drain of high-side MOSFET

12 to 15, 28, 35

Power ground

16 to 26

Switch node of the power stage

27, 33

GL

Low-side gate signal

29

Supply voltage for internal gate driver

30

THWn

Thermal warning open drain output

31

DSBL#

Disable pin. Active low

ORDERING INFORMATION

PART NUMBER

PACKAGE

MARKING CODE

OPTION

SiC620RCD-T1-GE3

PowerPAK MLP55-31L

SiC620R

5 V PWM optimized

SiC620ARCD-T1-GE3

PowerPAK MLP55-31L

SiC620AR

3.3 V PWM optimized

SiC620RDB / SiC620ARDB

Reference board

C

GND

BOOT

PHASE

V

IN

GH

PWM

ZCD_EN#

V

CIN

Top view

Bottom view

C

GND

BOOT

PHASE

V

IN

HG

PWM

ZCD_EN#

V

CIN

35

PGND

34

VIN

32

CGND

GL

2

1

31

29

30

28 27 26 25 24

4

3

6

5

8

7

15

14

13

12

11

10

9

2

1

4

3

6

5

8

7

15 14 13 12

11 10

9

24 25 26 27 28 29 30 31

V

33

GL

V

V

V

V

V

V

V

23 V

SWH

22 V

SWH

21 V

SWH

20 V

SWH

19 V

SWH

16 V

SWH

18 V

SWH

17 V

SWH

15