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5962F0721401VZC Datasheet(PDF) 7 Page - Texas Instruments |
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5962F0721401VZC Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 58 page  VDR DR GND + - + - ADC08D1520QML-SP www.ti.com SNAS420O – JANUARY 2008 – REVISED MARCH 2013 Pin Descriptions and Equivalent Circuits (continued) Pin Functions Pin No. Symbol Equivalent Circuit Description 83 / 78 DI7 − / DQ7− 84 / 77 DI7+ / DQ7+ 85 / 76 DI6 − / DQ6− 86 / 75 DI6+ / DQ6+ 89 / 72 DI5 − / DQ5− 90 / 71 DI5+ / DQ5+ I- and Q- channel LVDS Data Outputs that are not delayed in 91 / 70 DI4 − / DQ4− the output demultiplexer. Compared with the DId and DQd 92 / 69 DI4+ / DQ4+ outputs, these outputs represent the later time samples. 93 / 68 DI3 − / DQ3− These outputs should always be terminated with a 100 Ω 94 / 67 DI3+ / DQ3+ differential resistor. 95 / 66 DI2 − / DQ2− 96 / 65 DI2+ / DQ2+ 100 / 61 DI1 − / DQ1− 101 / 60 DI1+ / DQ1+ 102 / 59 DI0 − / DQ0− 103 / 58 DI0+ / DQ0+ 104 / 57 DId7 − / DQd7− 105 / 56 DId7+ / DQd7+ 106 / 55 DId6 − / DQd6− 107 / 54 DId6+ / DQd6+ 111 / 50 DId5 − / DQd5− I- and Q- channel LVDS Data Outputs that are delayed by 112 / 49 DId5+ / DQd5+ one CLK cycle in the output demultiplexer. Compared with the 113 / 48 DId4 − / DQd4− DI and DQ outputs, these outputs represent the earlier time 114 / 47 DId4+ / DQd4+ sample. These outputs should always be terminated with a 115 / 46 DId3 − / DQd3− 100 Ω differential resistor. In Non Demux Mode, these outputs 116 / 45 DId3+ / DQd3+ are disabled and are high impedance. When disabled, these 117 / 44 DId2 − / DQd2− outputs must be left floating. 118 / 43 DId2+ / DQd2+ 122 / 39 DId1 − / DQd1− 123 / 38 DId1+ / DQd1+ 124 / 37 DId0 − / DQd0− 125 / 36 DId0+ / DQd0+ Out Of Range output. A differential high at these pins indicates that the differential input is out of range ±VIN/2 as 79 OR+/DCLK2+ programmed by the FSR pin in Non-Extended Control Mode 80 OR-/DCLK2- or the Input Full-Scale Voltage Adjust register setting in the Extended Control Mode). DCLK2 is the exact mirror of DCLK and should output the same signal at the same rate. Data Clock. Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. In 1:2 Demultiplexed Mode, this signal is at 1/2 the input clock rate in SDR Mode and at 1/4 the input clock rate in the DDR Mode. By default, the DCLK outputs are not active during the termination resistor trim section of the calibration cycle. If a system requires DCLK to run continuously during a calibration cycle, the termination 81 DCLK- resistor trim portion of the cycle can be disabled by setting 82 DCLK+ the Resistor Trim Disable (RTD) bit to logic high in the Extended Configuration Register (address 9h). This disables all subsequent termination resistor trims after the initial trim which occurs during the power on calibration. Therefore, this output is not recommended as a system clock unless the resistor trim is disabled. When the device is in the Non- Demultiplexed Mode, DCLK can only be in DDR Mode and the signal is at 1/2 the input clock rate. 2, 5, 8, 13, 16, 17, 20, VA Analog power supply pins. Bypass these pins to ground. 25, 28, 33, 128 40, 51, 62, Output Driver power supply pins. Bypass these pins to DR 73, 88, 99, VDR GND. 110, 121 1, 6, 9, 12, GND Ground return for VA. 21, 24, 27 Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC08D1520QML-SP |
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