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NS32FX16-15 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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NS32FX16-15 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 88 page 10 Product Introduction (Continued) Below is a summary of the instructions that are directly ap- plicable to graphics along with their intended use Instruction Application BBAND The BITBLT group of instructions provide a BBOR method of quickly imaging characters BBFOR creating patterns windowing and other BBXOR block oriented effects BBSTOD BITWT EXTBLT MOVMP Move Multiple Pattern is a very fast instruction for clearing memory and drawing patterns and lines TBITS Test Bit String will measure the length of 1’s or 0’s in an image supporting many data compression methods (RLL) TBITS may also be used to test for boundaries of images SBITS Set Bit String is a very fast instruction for filling objects outline characters and drawing horizontal lines The TBITS and SBITS instructions support Group 3 and Group 4 CCITT standards for compression and decompression algorithms SBITPS Set Bit Perpendicular String is a very fast instruction for drawing vertical horizontal and 45 lines In printing applications SBITS and SBITPS may be used to express portrait and landscape respectively from the same compressed font data The size of the character may be scaled as it is drawn SBIT The Bit group of instructions enable single CBIT pixels anywhere in memory to be set TBIT cleared tested or inverted IBIT INDEX The INDEX instruction combines a multiply- add sequence into a single instruction This provides a fast translation of an X-Y address to a pixel relative address 20 Architectural Description 21 REGISTER SET The NS32FX16 has 23 internal registers and a 384-byte RAM array 17 of these registers belong to the CPU portion of the device and are addressed either implicitly by specific instructions or through the register addressing mode The other 6 control the operation of the DSP Module and are memory mapped Figure 2-1 shows the NS32FX16 internal registers CPU Registers General Purpose w 32 Bits x R0–R7 Address PC SP0 SP1 FP SB INTBASE MOD Processor Status PSR Configuration CFG Peripherals Registers DSP Module w 32 Bits x A Y O DPTR CPTR CTL ST RAM Array C 0 –C 95 FIGURE 2-1 NS32FX16 Internal Registers 7 |
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