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LP2994M Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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LP2994M Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 15 page Block Diagram 20045903 Description The LP2994 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-3. The output, V TT is capable of sinking and sourcing current while regulating the output voltage equal to V DDQ / 2. The output stage has been designed to maintain excellent load regula- tion while preventing shoot through. The LP2994 also incor- porates two distinct power rails which separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipa- tion. It also permits the LP2994 to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII). Series Stub Termination Logic (SSTL) was created to im- prove signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most com- mon form of termination is Class II single parallel termina- tion. This involves one R S series resistor from the chipset to the memory and one R T termination resistor. Typical values for R S and RT are 25 Ohms, although these can be changed to scale the current requirements from the LP2994. This implementation can be seen below in Figure 2. 20045931 FIGURE 2. SSTL Termination Scheme www.national.com 7 |
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