KA7543

8

Dimming Control Stage

Figure 5. Dimming Control Stage

The condition for full dimming is when the Vdm voltage is 2V and the condition for full lighting is when the Vdm voltage is

0V. Dimming operation starts when Vcs becomes 4V and the change rate of dimming is determined by the capacitor

connected to the Cdm pin. The more smooth dimming can be accomplished by the larger capacitor connected to the Cdm pin.

If the Vdm pin voltage is higher than 5V, then the output drive stage remains in off state. Dimming control and output drive on/

off control can be achieved with only one pin.

Output Drive Stage

Figure 6. Output Drive Stage

OUT1 and OUT2 are complementary and there is 1.4us dead time for the ZVS operation. The structure of output stage is the

totem-pole output stage. For the high side MOSFET drive, a pulse transformer is necessary.

No Lamp Protection

If the Vld pin voltage is lower than 1V, it means that there is no lamp connected. On no lamp condition, the output drive stage

is in off state.

9

Switch

-

+

+

+

-

2V

20k

Ω

Mirror

Dimmer

idr

is-id

id

+

-

Vdm

11

is

To error amp (+)

5V

Cdm

To output

CURRENT

AMPLIFIER

DIMMING

CONTROL

1

OUT1

14

OUT2

From oscillator

Q

Frequency

divider

Output

stage

From protection output from uvlo