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MT40A512M16JY-083E Datasheet(PDF) 90 Page - Micron Technology |
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MT40A512M16JY-083E Datasheet(HTML) 90 Page - Micron Technology |
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90 / 358 page  A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is fixed at 0, 1, 2, 3, T, T, T, T) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01 3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena- bled. Figure 32: MPR READ-to-WRITE Timing T0 T1 T2 DQ DQS_t, DQS_c tMPRR Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 DES DES DES DES WRITE DES DES Command DES READ DES DES DES DES Valid Valid Valid Valid Add2 Valid Valid Valid Add1 Valid Valid Valid Valid Address CKE PL3 + AL + CL UI2 UI3 UI0 UI1 UI4 UI5 UI6 UI7 CK_t CK_c Don’t Care Time Break Notes: 1. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t Care" when MR0 A[1:0] = 00 and must be 1b when MR0 A[1:0] = 01 2. Address setting: BA1 and BA0 indicate the MPR location A[7:0] = data for MPR BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care" 3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena- bled. MPR Writes MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0]. Data bus inversion (DBI) is not allowed during MPR WRITE operation. The DRAM will maintain the new written values unless re-initialized or there is power loss. The following steps are required to use the MPR to write to mode register MPR Page 0. 1. The DLL must be locked if enabled. 2. Precharge all; wait until tRP is satisfied. 3. MRS command to MR3[2] = 1 (enable MPR data flow) and MR3[1:0] = 00 (MPR Page 0); writes to 01, 10, and 11 are not allowed. 4. tMRD and tMOD must be satisfied. 8Gb: x8, x16 Automotive DDR4 SDRAM Multipurpose Register CCMTD-1406124318-10419 8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2016 Micron Technology, Inc. All rights reserved. |
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