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MT40A512M16JY-083E Datasheet(PDF) 75 Page - Micron Technology |
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MT40A512M16JY-083E Datasheet(HTML) 75 Page - Micron Technology |
75 / 358 page Command Address Latency DDR4 supports the command address latency (CAL) function as a power savings fea- ture. This feature can be enabled or disabled via the MRS setting. CAL timing is defined as the delay in clock cycles (tCAL) between a CS_n registered LOW and its correspond- ing registered command and address. The value of CAL in clocks must be programmed into the mode register (see MR1 Register Definition table) and is based on the equation tCK(ns)/tCAL(ns), rounded up in clocks. Figure 20: CAL Timing Definition CLK CMD/ADDR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CS_n tCAL CAL gives the DRAM time to enable the command and address receivers before a com- mand is issued. After the command and the address are latched, the receivers can be disabled if CS_n returns to HIGH. For consecutive commands, the DRAM will keep the command and address input receivers enabled for the duration of the command se- quence. Figure 21: CAL Timing Example (Consecutive CS_n = LOW) CLK CMD/ADDR 123456789 10 11 12 CS_n 8Gb: x8, x16 Automotive DDR4 SDRAM Command Address Latency CCMTD-1406124318-10419 8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2016 Micron Technology, Inc. All rights reserved. |
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