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MT40A512M16HA-083EIT Datasheet(PDF) 93 Page - Micron Technology |
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MT40A512M16HA-083EIT Datasheet(HTML) 93 Page - Micron Technology |
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93 / 373 page  Table 31: MPR Readout Serial Format (Continued) Serial UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 DQ9 01111111 DQ10 0 1 1 1 1 1 1 1 DQ11 0 1 1 1 1 1 1 1 DQ12 0 1 1 1 1 1 1 1 DQ13 0 1 1 1 1 1 1 1 DQ14 0 1 1 1 1 1 1 1 DQ15 0 1 1 1 1 1 1 1 MPR Readout Parallel Format Parallel format implies that the MPR data is returned in the first data UI and then repea- ted in the remaining UIs of the burst, as shown in the table below. Data pattern location 0 is the only location used for the parallel format. RD/RDA from data pattern locations 1, 2, and 3 are not allowed with parallel data return mode. In this example, the pattern programmed in the data pattern location 0 is 0111 1111. The x4 configuration only out- puts the first four bits (0111 in this example). For the x16 configuration, the same pat- tern is repeated on both the upper and lower bytes. Table 32: MPR Readout – Parallel Format Parallel UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 x4 Device DQ0 00000000 DQ1 11111111 DQ2 11111111 DQ3 11111111 x8 Device DQ0 00000000 DQ1 11111111 DQ2 11111111 DQ3 11111111 DQ4 11111111 DQ5 11111111 DQ6 11111111 DQ7 11111111 x16 Device DQ0 00000000 DQ1 11111111 DQ2 11111111 DQ3 11111111 DQ4 11111111 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register 09005aef861d1d4a 8gb_ddr4_dram.pdf - Rev. G 1/17 EN 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. |
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