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MT40A512M8 Datasheet(PDF) 51 Page - Micron Technology |
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MT40A512M8 Datasheet(HTML) 51 Page - Micron Technology |
51 / 365 page Mode Register 2 Mode register 2 (MR2) controls various device operating modes as shown in the follow- ing register definition table. Not all settings listed may be available on a die; only set- tings required for speed bin support are available. MR2 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The map- ping of address pins during the MRS command is shown in the following MR2 Register Definition table. Table 13: Address Pin Mapping Address bus BG1 BG0 BA1 BA0 A17 RAS _n CAS _n WE _n A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register 21 20 19 18 17 – – – 13 12 11 10 9876543210 Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command. Table 14: MR2 Register Definition Mode Register Description 21 RFU 0 = Must be programmed to 0 1 = Reserved 20:18 MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU 17 N/A on 4Gb and 8Gb, RFU 0 = Must be programmed to 0 1 = Reserved 13 RFU 0 = Must be programmed to 0 1 = Reserved 12 WRITE data bus CRC 0 = Disabled 1 = Enabled 4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2 09005aef84af6dd0 4gb_ddr4_dram.pdf - Rev. G 1/17 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. |
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