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MT40A512M8RH-083E Datasheet(PDF) 39 Page - Micron Technology |
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MT40A512M8RH-083E Datasheet(HTML) 39 Page - Micron Technology |
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39 / 365 page  Figure 13: RESET Procedure at Power Stable Condition CKE R TT BG, BA tPW_RESET_S CK_t, CK_c Command Note 1 Note 1 Td Tc Don’t Care Time Break tIS ODT Th tMRD tMOD MRS MRS Valid Valid tMRD tMRD MRS MRx MRx MRx MRS MRx Ti Tj Tk RESET_n T = 500μs Valid Te Ta Tb Tf ZQCL tIS Static LOW in case R TT(NOM) is enabled at time Tg, otherwise static HIGH or LOW tIS tIS tXPR Valid T (MIN) = 10ns V DD, VDDQ V PP tDLLK tZQinit tCKSRX Tg Notes: 1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL commands. 2. MRS commands must be issued to all mode registers that have defined settings. 3. In general, there is no specific sequence for setting the MRS locations (except for de- pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0, for example). 4. TEN is not shown; however, it is assumed to be held LOW. Uncontrolled Power-Down Sequence In the event of an uncontrolled ramping down of VPP supply, VPP is allowed to be less than VDD provided the following conditions are met: • Condition A: VPP and VDD/VDDQ are ramping down (as part of turning off) from nor- mal operating levels. • Condition B: The amount that VPP may be less than VDD/VDDQ is less than or equal to 500mV. • Condition C: The time VPP may be less than VDD is ≤10ms per occurrence with a total accumulated time in this state ≤100ms. 4Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure 09005aef84af6dd0 4gb_ddr4_dram.pdf - Rev. G 1/17 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. |
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