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MT40A1G8 Datasheet(PDF) 46 Page - Micron Technology |
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MT40A1G8 Datasheet(HTML) 46 Page - Micron Technology |
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46 / 373 page  Table 7: MR0 Register Definition (Continued) Mode Register Description 8 DLL reset 0 = No 1 = Yes 7 Test mode (TM) – Manufacturer use only 0 = Normal operating mode, must be programmed to 0 12, 6:4, 2 CAS latency (CL) – Delay in clock cycles from the internal READ command to first data-out 00000 = 9 clocks1 00001 = 10 clocks 00010 = 11 clocks1 00011 = 12 clocks 00100 = 13 clocks1 00101 = 14 clocks 00110 = 15 clocks1 00111 = 16 clocks 01000 = 18 clocks 01001 = 20 clocks 01010 = 22 clocks 01011 = 24 clocks 01100 = 23 clocks1 01101 = 17 clocks1 01110 = 19 clocks1 01111 = 21 clocks 1 10000 = 25 clocks (3DS use only) 10001 = 26 clocks 10010 = 27 clocks (3DS use only) 10011 = 28 clocks 10100 = 29 clocks1 10101 = 30 clocks 10110 = 31 clocks1 10111 = 32 clocks 3 Burst type (BT) – Data burst ordering within a READ or WRITE burst access 0 = Nibble sequential 1 = Interleave 1:0 Burst length (BL) – Data burst size associated with each read or write access 00 = BL8 (fixed) 01 = BC4 or BL8 (on-the-fly) 10 = BC4 (fixed) 11 = Reserved Notes: 1. Not allowed when 1/4 rate gear-down mode is enabled. 2. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28 clocks and RTP should be set to 14 clocks. 8Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0 09005aef861d1d4a 8gb_ddr4_dram.pdf - Rev. G 1/17 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. |
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