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IDT7054S35PRFB Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7054S35PRFB Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 11 page 1 ©2001 Integrated Device Technology, Inc. NOVEMBER 2001 DSC 3241/11 IDT7054S/L .eatures x x x x x High-speed access – Commercial: 20/25/35ns (max.) – Industrial: 25ns (max.) – Military: 25/35ns (max.) x x x x x Low-power operation – IDT7054S Active: 750mW (typ.) Standby: 7.5mW (typ.) – IDT7054L Active: 750mW (typ.) Standby: 1.5mW (typ.) x x x x x True FourPort memory cells which allow simultaneous access of the same memory locations x x x x x Fully asynchronous operation from each of the four ports: P1, P2, P3, and P4 x x x x x TTL-compatible; single 5V (±10%) power supply x x x x x Available in 128 pin Thin Quad Flatpack and 108 pin PGA packages x x x x x Industrial temperature range (–40°C to +85°C) is available for selected speeds Description The IDT7054 is a high-speed 4K x 8 FourPort™ Static RAM designed to be used in systems where multiple access into a common RAM is required.ThisFourPortStaticRAMoffersincreasedsystemperformance inmultiprocessorsystemsthathaveaneedtocommunicateinrealtimeand alsooffersaddedbenefitforhigh-speedsystemsinwhichmultipleaccess is required in the same cycle. The IDT7054 is also designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to .unctional Block Diagram HIGH-SPEED 4K x 8 FourPortTM STATIC RAM MEMORY ARRAY COLUMN I/O PORT 1 ADDRESS DECODE LOGIC PORT 2 ADDRESS DECODE LOGIC COLUMN I/O COLUMN I/O PORT 4 ADDRESS DECODE LOGIC PORT 3 ADDRESS DECODE LOGIC COLUMN I/O R/WP1 I/O0P1-I/O7P1 CEP1 OEP1 A0P1 -A11P1 R/WP2 CEP2 OEP2 3241 drw 01 I/O0P2-I/O7P2 A0P2 -A11P2 R/WP4 I/O0P4-I/O7P4 CEP4 OEP4 A0P4 -A11P4 R/WP3 CEP3 OEP3 I/O0P3-I/O7P3 A0P3 -A11P3 |
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