9

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Figure 2. Writing to Offset Registers

LD

WEN

WCLK

Selection

0

0

Writingtooffsetregisters:

Empty Offset

FullOffset

0

1

No Operation

1

0

Write Into FIFO

1

1

No Operation

Figure 3. Offset Register Location and Default Values

SIGNAL DESCRIPTIONS:

INPUTS:

Data inputs for 18-bit wide data.

CONTROLS:

RESET (

RS)

Reset is accomplished whenever the Reset (

RS) input is taken to a LOW

state. During reset, both internal read and write pointers are set to the first

location. A reset is required after power-up before a write operation can take

place. The Half-Full Flag (

HF)andProgrammableAlmost-FullFlag(PAF)will

PAE)will

FF) will reset to HIGH. The Empty

Flag(

EF)willresettoLOWinIDTStandardmodebutwillresettoHIGHinFWFT

mode. During reset, the output register is initialized to all zeros and the offset

registers are initialized to their default values.

WRITE CLOCK (WCLK)

A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock

(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH

transitionofWCLK.

The Write and Read Clocks can be asynchronous or coincident.

WRITE ENABLE (

WEN)

When the

WENinput isLOW,datamaybeloadedintotheFIFORAMarray

on the rising edge of every WCLK cycle if the device is not full. Data is stored

in the RAM array sequentially and independently of any ongoing read

operation.

When

WENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK

cycle.

To prevent data overflow in the IDT Standard Mode,

FF will go LOW,

inhibiting further write operations. Upon the completion of a valid read cycle,

FF will go HIGH allowing a write to occur. TheFF flag is updated on the rising

edge of WCLK.

To prevent data overflow in the FWFT mode,

IR will go HIGH, inhibiting

further write operations. Upon the completion of a valid read cycle,

IR will go

LOWallowingawritetooccur. The

IRflagisupdatedontherisingedgeofWCLK.

WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.

READ CLOCK (RCLK)

DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead

Clock (RCLK), when Output Enable (

OE) is set LOW.

The Write and Read Clocks can be asynchronous or coincident.

READ ENABLE (

REN)

WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput

register on the rising edge of every RCLK cycle if the device is not empty.

Whenthe

RENinputisHIGH,theoutputregisterholdsthepreviousdataand

the previous data value.

word written to an empty FIFO, must be requested using

REN. When the last

word has been read from the FIFO, the Empty Flag (

EF)willgoLOW,inhibiting

further read operations.

RENisignoredwhentheFIFOisempty. Onceawrite

is performed,

EFwillgoHIGHallowingareadtooccur. The EFflagisupdated

on the rising edge of RCLK.

IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes

after the first write.

RENdoesnotneedtobeassertedLOW. Inordertoaccess

all other words, a read must be executed using

REN. TheRCLKLOWtoHIGH

transition after the last word has been read from the FIFO, Output Ready (

OR)

will go HIGH with a true read (RCLK with

REN=LOW),inhibitingfurtherread

operations.

REN is ignored when the FIFO is empty.

OUTPUT ENABLE (

OE)

When Output Enable (

OE) is enabled (LOW), the parallel output buffers

receivedatafromtheoutputregister.When

OEisdisabled(HIGH),theQoutput

data bus is in a high-impedance state.

LOAD (

LD)

The IDT72V205/72V215/72V225/72V235/72V245 devices contain two

12-bit offset registers with data on the inputs, or read on the outputs. When the

Load (

LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is

writtenintotheEmptyOffsetregisteronthefirstLOW-to-HIGHtransitionofthe

Write Clock (WCLK). When the

LD pin and WEN are held LOW then data is

written into the Full Offset register on the second LOW-to-HIGH transition of

WCLK. The third transition of WCLK again writes to the Empty Offset register.

However,writingalloffsetregistersdoesnothavetooccuratonetime.One

or two offset registers can be written and then by bringing the

LDpinHIGH,the

FIFO is returned to normal read/write operation. When the

LDpinissetLOW,

and

WEN is LOW, the next offset register in sequence is written.

EMPTY OFFSET REGISTER

17

11

0

001FH (72V205) 003FH (72V215):

007FH (72V225/72V235/72V245)

FULL OFFSET REGISTER

17

11

0

DEFAULT VALUE

DEFAULT VALUE

001FH (72V205) 003FH (72V215):

007FH (72V225/72V235/72V245)

4294 drw 04

NOTE:

1. Any bits of the offset register not being programmed should be set to zero.

NOTE:

1. The same selection sequence applies to reading from the registers.

REN is enabled and

read is performed on the LOW-to-HIGH transition of RCLK.