IDT71V2578YSA150PF datasheet(9/22 Pages) IDT

Part #	IDT71V2578YSA150PF

Description	128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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9 / 22 page

6.42

IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

9

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Figure 2. Lumped Capacitive Load, Typical Derating

Figure 1. AC Test Load

AC Test Load

AC Test Conditions

(VDDQ = 2.5V)

NOTE:

1. The

LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while

ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

VDDQ/2

50

Ω

I/O

Z0 =50

Ω

4876 drw 06

,

1

2

3

4

20 30 50

100

200

∆tCD

(Typical, ns)

Capacitance (pF)

80

5

6

4876 drw 07

,

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

|ILI|

Input Leakage Current

VDD = Max., VIN = 0V to VDD

___

5

µA

|ILZZ|

ZZ

LBO and JTAG Input Leakage Current(1)

VDD = Max., VIN = 0V to VDD

___

30

µA

|ILO|

Output Leakage Current

VOUT = 0V to VDDQ, Device Deselected

___

5

µA

VOL

Output Low Voltage

IOL = +6mA, VDD = Min.

___

0.4

V

VOH

Output High Voltage

IOH = -6mA, VDD = Min.

2.0

___

V

4876 tbl 08

Symbol

Parameter

Test Conditions

150MHz

133MHz

Unit

Com'l

Ind

Com'l

Ind

IDD

Operating Power Supply

Current

Device Selected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)

295

305

250

260

mA

ISB1

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)

30

35

30

35

mA

ISB2

Clock Running Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3)

105

115

100

110

mA

IZZ

Full Sleep Mode Supply

Current

ZZ > VHD, VDD = Max.

30

35

30

35

mA

4876 tbl 09

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

0 to 2.5V

2ns

(VDDQ/2)

See Figure 1

4876 tbl 10

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