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IDT821054 Datasheet(PDF) 13 Page - Integrated Device Technology |
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IDT821054 Datasheet(HTML) 13 Page - Integrated Device Technology |
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13 / 45 page  13 IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE RANGE channels’ SI1 and SI2 status changes can be cleared by applying a read operation to GREG9. If SB1, SB2 and SB3 pins are configured as inputs, a read operation to GREG10, GREG11 and GREG12 clears the interrupt generated by the corresponding SB port of all four channels. A read operation to LREG4 clears all 7 interrupt sources of the specified channel. 2.6 DEBOUNCE FILTERS For each channel, the IDT821054 provides two debounce filter circuits: Debounced Switch Hook (DSH) Filter for the SI1 signal and Ground Key (GK) Filter for the SI2 signal. See Figure - 5 for details. The two debounce filters are used to buffer the input signals on SI1 and SI2 pins before changing the state of the SLIC Debounced Input SI1/SI2 Register (GREG9). The Frame Sync (FS) signal is necessary for both DSH and GK filters. The DSH[3:0] bits in LREG3 are used to program the debounce period of the SI1 input of the corresponding channel. The DSH filter is initially clocked at half of the frame sync rate (250 µs). Any data changing at this sample rate resets a counter that clocks at the rate of 2 ms. The value of the counter is programmable from 0 to 30 via LREG3. The debounced SI1 signals of Channel 4 to 1 are written to the SIA[3:0] bits in GREG9. The corresponding SIA bit will not be updated until the value of the counter is reached. The SI1 pin usually contains the SLIC switch hook status. The GK[3:0] bits in LREG3 are used to program the debounce interval of the SI2 input of the corresponding channel. The debounced SI2 signals of Channel 4 to 1 are written to the SIB[3:0] bits in GREG9. The GK debounce filter consists of a six-state up/down counter that ranges between 0 and 6. This counter is clocked by the GK timer at the sampling period of 0-30 ms, which is programmed via LREG3. If the sampled value is low, the value of the counter will be decremented by each clock pulse. If the sampled value is high, the value of the counter is incremented by each clock pulse. When the value increases to 6, it sets a latch whose output is routed to the corresponding SIB bit. If the value decreases to 0, the latch will be cleared and the output bit will be set to 0. In other cases, the latch and the SIB status remain in their previous state without being changed. In this way, at least six consecutive GK clocks with the debounce input remaining at the same state can effect an output change. Figure - 5 Debounce Filter 2.7 CHOPPER CLOCK The IDT821054 provides two programmable chopper clock outputs CHCLK1 and CHCLK2. They can be used to drive the power supply switching regulators on SLICs. The two chopper clocks are synchronous to MCLK. The CHCLK1 outputs a signal which clock cycle is programmable from 2 to 28 ms. The CHCLK2 outputs a signal which frequency can be 256 kHz, 512 kHz or 16.384 MHz. The frequencies of the two chopper clocks are programmed by global register GREG5. 2.8 DUAL TONE AND RING GENERATION The IDT821054 provides two tone generators (tone generator 0 and tone generator 1) for each channel. They can produce signals such as test tone, DTMF, dial tone, busy tone, congestion tone and Caller-ID Alerting Tone, and output it to the VOUT pin. The dual tone generators of each channel can be enabled by setting the TEN0 and TEN1 bits in LREG10 to ‘1’respectively. The frequency and amplitude of the tone signal are programmed by the Coe-RAM. The frequency and amplitude coefficients are calculated by the following formulas: Frequency coefficient = 32767 ∗ cos(f / 8000 ∗ 2 ∗ π) Amplitude coefficient = A ∗ 32767 ∗ sin(f / 8000 ∗ 2 ∗ π) Herein, 'f' is the desired frequency of the tone signal, 'A' is the scaling parameter of the amplitude. The range of 'A' is from 0 to 1. A = 1, corresponds to the maximum amplitude of 1.57 V. A = 0, corresponds to the minimum amplitude of 0 V. It is a linear relationship between 'A' and the amplitude. That is, if A= β ( 0<β<1), the amplitude will be 1.57 ∗ β (V). The frequency range is from 25 Hz to 3400 Hz. The frequency tolerances are as the following: 25 Hz < f < 40 Hz, tolerance < ±12% DQ DQ DQ DQ E DQ DSH[3:0] Debounce Period (0-30 ms) DQ GK[3:0] Debounce Interval (0-30 ms) up/ down Q 6 states Up/down Counter 7 bit Debounce Counter 7 bit Debounce Counter = 0 ≠ 0 GK SIB SIA SI1 4 kHz SI2 RST FS/2 |
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