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IDT72V205 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT72V205
Description  3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V205 Datasheet(HTML) 1 Page - Integrated Device Technology

 
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FEBRUARY 2002
IDT72V205, IDT72V215,
IDT72V225, IDT72V235,
IDT72V245
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4294/3
3.3 VOLT CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
FEATURES:
••••• 256 x 18-bit organization array (IDT72V205)
••••• 512 x 18-bit organization array (IDT72V215)
••••• 1,024 x 18-bit organization array (IDT72V225)
••••• 2,048 x 18-bit organization array (IDT72V235)
••••• 4,096 x 18-bit organization array (IDT72V245)
••••• 10 ns read/write cycle time
••••• 5V input tolerant
••••• IDT Standard or First Word Fall Through timing
••••• Single or double register-buffered Empty and Full flags
••••• Easily expandable in depth and width
••••• Asynchronous or coincident Read and Write Clocks
••••• Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
••••• Half-Full flag capability
••••• Output enable puts output data bus in high-impedanc state
••••• High-performance submicron CMOS technology
••••• Available in a 64-lead thin quad flatpack (TQFP/STQFP)
••••• Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
OFFSET REGISTER
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF/(WXO)
READ POINTER
READ CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
WEN
WCLK
D0-D17
LD
RS
(
HF)/WXO
WXI
REN
RCLK
OE
Q0-Q17
RXO
RXI
FL
4294 drw 01
DESCRIPTION:
The IDT72V205/72V215/72V225/72V235/72V245 are functionally com-
patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs are applicable
forawidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,Local
Area Networks (LANs), and interprocessor communication.
TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled
by a free-running clock (WCLK), and an input enable pin (
WEN). Data is read
into the synchronous FIFO on every clock when
WENisasserted.Theoutput
port is controlled by another clock pin (RCLK) and another enable pin (
REN).
TheReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperation
orthetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.
An Output Enable pin (
OE) is provided on the read port for three-state control
oftheoutput.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(
EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty(
PAE)andAlmost-Full(PAF). Theoffsetloadingoftheprogram-


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