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IDT72V205 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72V205
Description  3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V205 Datasheet(HTML) 5 Page - Integrated Device Technology

 
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Commercial
Com'l & Ind'l(1)
Commercial
IDT72V205L10
IDT72V205L15
IDT72V205L20
IDT72V215L10
IDT72V215L15
IDT72V215L20
IDT72V225L10
IDT72V225L15
IDT72V225L20
IDT72V235L10
IDT72V235L15
IDT72V235L20
IDT72V245L10
IDT72V245L15
IDT72V245L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
100
66.7
50
MHz
tA
Data Access Time
2
6.5
2
10
2
12
ns
tCLK
Clock Cycle Time
10
15
20
ns
tCLKH
Clock HIGH Time
4.5
6
8
ns
tCLKL
Clock LOW Time
4.5
6
8
ns
tDS
DataSet-upTime
3
4
5
ns
tDH
Data Hold Time
0.5
1
1
ns
tENS
EnableSet-upTime
3
4
5
ns
tENH
Enable Hold Time
0.5
1
1
ns
tRS
Reset Pulse Width(2)
10
15
20
ns
tRSS
ResetSet-upTime
8
10
12
ns
tRSR
Reset Recovery Time
8
10
12
ns
tRSF
Reset to Flag and Output Time
15
15
20
ns
tOLZ
Output Enable to Output in Low-Z(3)
0—
0—
0—
ns
tOE
Output Enable to Output Valid
6
3
8
3
10
ns
tOHZ
Output Enable to Output in High-Z(3)
16
38
3
10
ns
tWFF
Write Clock to Full Flag
6.5
10
12
ns
tREF
Read Clock to Empty Flag
6.5
10
12
ns
tPAFA
Clock to Asynchronous Programmable Almost-Full Flag
17
20
22
ns
tPAFS
Write Clock to Synchronous ProgrammableAlmost-Full Flag
8
10
12
ns
tPAEA
Clock to Asynchronous Programmable Almost-Empty Flag
17
20
22
ns
tPAES
Read Clock to Synchronous Programmable Almost-Empty Flag
8
10
12
ns
tHF
Clock to Half-Full Flag
17
20
22
ns
tXO
Clock to Expansion Out
6.5
10
12
ns
tXI
Expansion In Pulse Width
3
6.5
8
ns
tXIS
Expansion In Set-Up Time
3
5
8
ns
tSKEW1
Skew time between Read Clock & Write Clock for
FF/IR
5—
6—
8—
ns
and
EF/OR
tSKEW2(4)
Skew time between Read Clock & Write Clock for
PAE
14
18
20
ns
and
PAF
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
OutputLoad
See Figure 1
AC TEST CONDITIONS
Figure 1. Output Load
* Includes jig and scope capacitances.
30pF*
330
3.3V
510
D.U.T.
4294 drw 03
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. tSKEW2 applies to synchronous
PAE and synchronous PAF only.


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