IDT72V205 datasheet(20/25 Pages) IDT

Part #	IDT72V205

Description	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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20 / 25 page

20

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Figure 25. Write Cycle Timing with Double Register-Buffered

FF (IDT Standard Mode)

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising

edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the

FF deassertion time may be delayed an extra WCLK cycle.

2.

LD = HIGH.

3. Select this mode by setting (

FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.

Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising

edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the

FF deassertion may be delayed an extra WCLK cycle.

2.

LD = HIGH.

3. Select this mode by setting (

FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.

WCLK

D0 - D17

WEN

FF

RCLK

REN

tDS

tWFF

DATA IN VALID

NO OPERATION

(1)

tSKEW1

4294 drw 25

tENS

tDH

tENH

1

2

tCLKH

tCLKL

tCLK

D0 - D17

WEN

RCLK

FF

REN

tENH

Q0 - Q17

DATA READ

NEXT DATA READ

DATA IN OUTPUT REGISTER

LOW

OE

tSKEW1

DATA WRITE

4294 drw 24

WCLK

NO WRITE

1

2

1

2

tDS

NO WRITE

tWFF

tA

tENS

tSKEW1

tDS

tA

Wd

(1)

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