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IDT72V205 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT72V205
Description  3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V205 Datasheet(HTML) 2 Page - Integrated Device Technology

 
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN CONFIGURATIONS
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
DESCRIPTION (CONTINUED)
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
4294 drw 02
mableflagsiscontrolledbyasimplestatemachine,andisinitiatedbyasserting
the Load pin (
LD). A Half-Full flag (HF) is available when the FIFO is used
in a single device configuration.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall-Through (FWFT) mode.
InIDTStandardMode,thefirstwordwrittentoanemptyFIFOwillnotappear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
RENandenablingarisingRCLKedge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
RENdoes
not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
FirstWordFallThroughmode(FWFT).The
XIandXOpinsareusedtoexpand
the FIFOs. In depth expansion configuration, First Load (
FL) is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
IDT’s high-speed submicron CMOS technology.


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