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ICPL2730 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. ICPL2730
Description  HIGH SPEED DUAL CHANNEL OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT
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Maker  ETC [List of Unclassifed Manufacturers]
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ICPL2730 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

   
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SWITCHING SPECIFICATIONS AT T
A = 25°C ( VCC = 5V Unless otherwise noted )
PARAMETER
SYM DEVICE
MIN TYP MAX UNITS
TEST CONDITION
Propagation Delay Time
ICPL2731
25
100
µs
I
F = 0.5mA,RL = 4.7kΩ
to Logic Low at Output
t
PHL
ICPL2730/1
0.5
2
µs
I
F = 12mA,RL = 270Ω
( fig 1 )( note 5 )
ICPL2730/1
4.0
20
µs
I
F = 1.6mA,RL = 2.2kΩ
Propagation Delay Time
ICPL2731
20
60
µs
I
F = 0.5mA,RL = 4.7kΩ
to Logic High at Output
t
PLH
ICPL2730/1
4
10
µs
I
F = 12mA,RL = 270Ω
( fig 1 )( note 5 )
ICPL2730/1
12
35
µs
I
F = 1.6mA,RL = 2.2kΩ
Common Mode Transient
Immunity at Logic High
CM
H
1000 10000
V/
µs
I
F = 0mA, VCM = 10VPP
Level Output ( fig 2 )( note 9 )
R
L = 2.2kΩ
Common Mode Transient
Immunity at Logic Low
CM
L
-1000 -10000
V/
µs
I
F= 1.6mA,VCM= 10VPP
Level Output ( fig 2 )( note 8 )
R
L = 2.2kΩ
NOTES:-
1.
Derate linearly above 70oC free air temperature at a rate of 0.5 mA/°C.
2.
Derate linearly above 70oC free air temperature at a rate of 0.9 mW/°C.
3.
Derate linearly above 70oC free air temperature at a rate of 0.6 mA/°C.
4.
Derate linearly above 35oC free air temperature at a rate of 1.7 mW/°C.
Output power = (Collector output) + (Supply output).
5.
Each channel.
6.
CURRENT TRANSFER RATIO is defined as the ratio of output collector current,I
O , to the forward LED
input current, I
F times 100%.
7.
Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
8.
Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dVcm/dt on
the trailing edge of the common mode pulse signal, V
CM to assure that the output will remain in Logic
Low state (i.e. V
O< 0.8V).Measured in volts per microsecond (V/µs).
9.
Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on
the leading edge of the common mode pulse V
CM to assure that the output will remain in a Logic High
state (i.e. V
O > 2.0V).Measured in volts per microsecond (V/µs).
10.
Device considered a two-terminal device: pins 1,2,3, and 4 shorted together and pins 5,6,7 and 8 shorted
together.
FIG.1 SWITCHING TEST CIRCUIT
2
I
F Monitor
0
I
F
V
O
1.5V
100
1.5V
5V
t
PHL
t
PLH
V
OL
R
L
V
O
C
L = 15pF
8
7
6
5
PULSE
GENERATOR
Z
O = 50Ω
t
r = 5ns
I
F
1
4
3
10% Duty Cycle
1/f < 100
µs
5V
DB92018-AAS/A2
7/12/00


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