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XR28V384IM48-0A Datasheet(PDF) 1 Page - Exar Corporation |
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XR28V384IM48-0A Datasheet(HTML) 1 Page - Exar Corporation |
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1 / 42 page  Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XR28V384 3.3V QUAD LPC UART WITH 128-BYTE FIFO NOVEMBER 2013 REV. 1.0.0 GENERAL DESCRIPTION The XR28V384 (V384) is a quad Universal Asynchronous Receiver and Transmitter (UART) for the Intel Low Pin Count (LPC) bus interface. This device can replace or supplement a Super I/O device to add additional serial ports to the system. The V384 UARTs support any 16-bit I/O address supported by the system. The register set is based on the industry standard 16550 UART, so the V384 operates with the standard serial port drivers without requiring a custom driver to be installed. The 128 byte Transmit and Receive FIFOs reduce CPU overhead and minimize the chance of buffer overflow and data loss. In addition to the 16550 UART registers, there are also Configuration register set where enhanced features such as the 9-bit (multidrop) mode, IrDA mode and the Watchdog Timer can be enabled. The V384 is available in a 48-pin TQFP package. APPLICATIONS Industrial and Embedded PCs Factory Automation and Process Controls Network Routers System Board Designs FEATURES 128 Byte Transmit and Receive FIFO Compliant to LPC 1.1 Specifications -40°C to +85°C Industrial Temp Operation Watchdog Timer with WDTOUT# signal 4 Independent UART channels ■ Programmable I/O mapped base addresses ■ Data rates up to 3 Mbps ■ Selectable RX FIFO interrupt trigger levels ■ Auto RS-485 Half-Duplex Control mode ■ Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity ■ IrDA mode and separate IRTXA# and IRRXA# pins for the first UART channel ■ 9-bit (Multidrop) mode External 24MHz/48MHz clock Single 3.3V Supply Voltage ( ±10% ) 5V tolerant inputs 48-TQFP package (7mm x 7mm) FIGURE 1. XR28V384 BLOCK DIAGRAM L P C B u s In te r fa c e T X F IF O ( Ir D A E n c o d e r ) M o d e m IO s C lo c k D iv id e r R X F IF O ( I r D A D e c o d e r ) R T S A # /P S _ C O N F _ 2 E /R S 4 8 5 D T R A # /P S _ 3 E 0 _ IR Q A C T S A # , D S R A # , C D A # , R IA # U A R T C h a n n e l A B a u d R a te G e n e r a to r S ta tu s a n d C o n tr o l R e g is te r s V C C G N D W D T O U T # C L K I N P C IR S T # L C L K L F R A M E # L A D [ 3 :0 ] S E R IR Q G lo b a l C o n f ig u r a t io n R e g is te r s W a tc h D o g T im e r T X A / P S _ 3 F 8 _ IR Q A IR T X A # R X A IR R X A # T X F IF O M o d e m IO s R X F IF O U A R T C h a n n e l B R T S B # /P S _ C O N F _ K E Y 1 / R S 4 8 5 D T R B # /P S _ 2 E 0 _ IR Q B C T S B # , D S R B # , C D B # , R IB # T X B / P S _ 2 F 8 _ IR Q B R X B T X F IF O M o d e m IO s R X F IF O U A R T C h a n n e l C R T S C # /P S _ C O N F _ K E Y 0 /R S 4 8 5 D T R C # / P S _ W D T C T S C # , D S R C # , C D C # , R IC # T X C / P S _ 3 E 8 _ IR Q C R X C T X F IF O M o d e m IO s R X F IF O U A R T C h a n n e l D R T S D # /R S 4 8 5 D T R D # C T S D # , D S R D # , C D D # , R ID # T X D / P S _ 2 E 8 _ IR Q D R X D B a u d R a te G e n e r a t o r S ta tu s a n d C o n tr o l R e g is te r s B a u d R a te G e n e r a to r S ta tu s a n d C o n tr o l R e g is t e r s B a u d R a te G e n e r a to r S ta tu s a n d C o n tr o l R e g is t e r s 3 . 3 V ± 1 0 % |
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