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XR16M654DIV-0B Datasheet(PDF) 7 Page - Exar Corporation |
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XR16M654DIV-0B Datasheet(HTML) 7 Page - Exar Corporation |
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7 / 58 page  XR16M654/654D 7 REV. 1.0.0 1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO INTB INTC INTD (N.C.) 10 26 32 12 37 43 21 49 55 14 48 54 18 63 69 O When 16/68# pin is HIGH for Intel bus inter- face, these ouputs become the interrupt outputs for channels B, C, and D. The out- put state is defined by the user through the software setting of MCR[3]. The interrupt outputs are set to the active mode when MCR[3] is set to a logic 1 and are set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, these outputs are unused and will stay at logic zero level. Leave these out- puts unconnected. INTSEL 38 - 65 67 87 I Interrupt Select (active high, input with internal pull-down). When 16/68# pin is HIGH for Intel bus inter- face, this pin can be used in conjunction with MCR bit-3 to enable or disable the INT A-D pins or override MCR bit-3 and enable the interrupt outputs. Interrupt outputs are enabled continuously when this pin is HIGH. MCR bit-3 enables and disables the interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continu- ous output. See MCR bit-3 description for full detail. This pin must be LOW in the Motorola bus interface mode. For the 64 pin packages, this pin is bonded to VCC internally in the XR16M654D so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the XR16M654 and therefore requires setting MCR bit-3 for enabling the interrupt output pins. TXRDYA# TXRDYB# TXRDYC# TXRDYD# - - - - - - - - - - - - - - - - 5 25 56 81 O UART channels A-D Transmitter Ready (active low). The outputs provide the TX FIFO/THR status for transmit channels A-D. See Table 5. If these outputs are unused, leave them unconnected. RXRDYA# RXRDYB# RXRDYC# RXRDYD# - - - - - - - - - - - - - - - - 100 31 50 82 O UART channels A-D Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channels A-D. See Table 5. If these outputs are unused, leave them unconnected. TXRDY# - - 39 35 45 O Transmitter Ready (active low). This output is a logically ANDed status of TXRDY# A- D. See Table 5. If this output is unused, leave it unconnected. RXRDY# - - 38 34 44 O Receiver Ready (active low). This output is a logically ANDed status of RXRDY# A-D. See Table 5. If this output is unused, leave it unconnected. Pin Description NAME 48-QFN PIN # 64-LQFP PIN # 68-PLCC PIN# 80-LQFP PIN # 100-QFP PIN # TYPE DESCRIPTION |
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