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LP3985IBL-2.9 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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LP3985IBL-2.9 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 17 page Block Diagram 10136401 Pin Description Name * micro SMD SOT Function V EN A1 3 Enable Input Logic, Enable High GND B2 2 Common Ground V OUT C1 5 Output Voltage of the LDO V IN C3 1 Input Voltage of the LDO BYPASS A3 4 Optional Bypass Capacitor for Noise Reduction * The pin numbering scheme for the micro SMD package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5. Connection Diagrams SOT 23-5 Package (MF) 5 Bump micro SMD Package (BPA05, BLA05, TLA05) 10136407 Top View See NS Package Number MF05A 10136470 Top View See NS Package Number BPA05, BLA05, TLA05 www.national.com 2 |
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