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AM29LV116DB-70FI Datasheet(PDF) 4 Page - Advanced Micro Devices |
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AM29LV116DB-70FI Datasheet(HTML) 4 Page - Advanced Micro Devices |
4 / 44 page Am29LV116D 3 TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 Standard Products .................................................................... 7 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8 Table 1. Am29LV116D Device Bus Operations ................................8 Requirements for Reading Array Data ..................................... 8 Writing Commands/Command Sequences .............................. 8 Program and Erase Operation Status ...................................... 9 Standby Mode .......................................................................... 9 Automatic Sleep Mode ............................................................. 9 RESET#: Hardware Reset Pin ................................................. 9 Output Disable Mode ................................................................ 9 Table 2. Am29LV116DT Top Boot Sector Address Table ..............10 Table 3. Am29LV116DB Bottom Boot Sector Address Table .........11 Autoselect Mode ..................................................................... 12 Table 4. Am29LV116D Autoselect Codes (High Voltage Method) ..12 Sector Protection/Unprotection ............................................... 12 Temporary Sector Unprotect .................................................. 12 Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 13 Figure 2. Temporary Sector Unprotect Operation........................... 14 Hardware Data Protection ...................................................... 14 Low VCC Write Inhibit .............................................................. 14 Write Pulse “Glitch” Protection ............................................... 14 Logical Inhibit .......................................................................... 14 Power-Up Write Inhibit ............................................................ 14 Common Flash Memory Interface (CFI) . . . . . . . 14 Table 5. CFI Query Identification String ..........................................15 Table 6. System Interface String .....................................................15 Table 7. Device Geometry Definition ..............................................16 Table 8. Primary Vendor-Specific Extended Query ........................16 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 17 Reading Array Data ................................................................ 17 Reset Command ..................................................................... 17 Autoselect Command Sequence ............................................ 17 Byte Program Command Sequence ....................................... 17 Unlock Bypass Command Sequence ..................................... 18 Figure 3. Program Operation .......................................................... 18 Chip Erase Command Sequence ........................................... 18 Sector Erase Command Sequence ........................................ 19 Erase Suspend/Erase Resume Commands ........................... 19 Figure 4. Erase Operation............................................................... 20 Command Definitions ............................................................. 21 Table 9. Am29LV116D Command Definitions ...............................21 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 22 DQ7: Data# Polling ................................................................. 22 Figure 5. Data# Polling Algorithm ................................................... 22 RY/BY#: Ready/Busy# ........................................................... 23 DQ6: Toggle Bit I .................................................................... 23 DQ2: Toggle Bit II ................................................................... 23 Reading Toggle Bits DQ6/DQ2 ............................................... 23 DQ5: Exceeded Timing Limits ................................................ 24 DQ3: Sector Erase Timer ....................................................... 24 Figure 6. Toggle Bit Algorithm........................................................ 24 Table 10. Write Operation Status ................................................... 25 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26 Figure 7. Maximum Negative Overshoot Waveform ...................... 26 Figure 8. Maximum Positive Overshoot Waveform........................ 26 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27 CMOS Compatible .................................................................. 27 Zero Power Flash ................................................................... 28 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 28 Figure 10. Typical ICC1 vs. Frequency ........................................... 28 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 11. Test Setup..................................................................... 29 Table 11. Test Specifications ......................................................... 29 Key to Switching Waveforms .................................................. 29 Figure 12. Input Waveforms and Measurement Levels ................. 29 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30 Read Operations .................................................................... 30 Figure 13. Read Operations Timings ............................................. 30 Hardware Reset (RESET#) .................................................... 31 Figure 14. RESET# Timings .......................................................... 31 Erase/Program Operations ..................................................... 32 Figure 15. Program Operation Timings.......................................... 33 Figure 16. Chip/Sector Erase Operation Timings .......................... 33 Figure 17. Data# Polling Timings (During Embedded Algorithms). 34 Figure 18. Toggle Bit Timings (During Embedded Algorithms)...... 34 Figure 19. DQ2 vs. DQ6................................................................. 35 Temporary Sector Unprotect .................................................. 35 Figure 20. Temporary Sector Unprotect Timing Diagram .............. 35 Figure 21. Sector Protect/Unprotect Timing Diagram .................... 36 Figure 22. Alternate CE# Controlled Write Operation Timings ...... 38 Erase and Programming Performance . . . . . . . 39 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 39 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 39 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40 TS 040—40-Pin Standard TSOP ............................................ 40 TSR040—40-Pin Reverse TSOP ........................................... 41 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42 Revision A (October 1997) ..................................................... 42 Revision B (October 1997) ..................................................... 42 Revision C (December 1997) ................................................. 42 Revision C+1 (January 1998) ................................................. 42 Revision C+2 (March 1998) .................................................... 42 Revision C+3 (August 1998) ................................................... 42 Revision D (January 1999) ..................................................... 42 Revision E (February 2, 2000) ................................................ 42 Revision E+1 (November 7, 2000) ......................................... 42 |
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