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AT17N256-10NC Datasheet(PDF) 5 Page - ATMEL Corporation

Part # AT17N256-10NC
Description  FPGA Configuration Memory
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT17N256-10NC Datasheet(HTML) 5 Page - ATMEL Corporation

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5
AT17N256/512/010/002/040
3020A–CNFG–04/10/03
DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
GND
Ground pin. A 0.2 µF decoupling capacitor between V
CC and GND is recommended.
VCC(SER_EN)
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V
CC.
V
CC
3.3V (±10%) Commercial and Industrial power supply pin.
NC
NC pins are No Connect pins, which are not internally bonded out to the die.
DC
DC pins are No Connect pins internally connected to the die. It is not recommended to
connect these pins to any external signal.
Pin Description
Name
I/O
AT17N256
AT17N512/
AT17N010
AT17N002
AT17N040
8
DIP/
SOIC
20
SOIC
8
DIP/
LAP
20
SOIC
8
LAP
20
SOIC
44
TQFP
44
TQFP
DATA
I/O
1
1
1
1
1
1
40
40
CLK
I
2
3
23
23
43
43
RESET/OE
I3
8
3
8
3
8
13
13
CE
I
4
10
410410
15
15
GND
5
11
511511
18
18
DC
O
6
13
613613
21
21
DC
O
23
23
VCC(SER_EN)
I
7
18
7
18718
35
35
VCC
8
20
8
20820
38
38


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