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AT17N256-10NC Datasheet(PDF) 8 Page - ATMEL Corporation

Part # AT17N256-10NC
Description  FPGA Configuration Memory
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT17N256-10NC Datasheet(HTML) 8 Page - ATMEL Corporation

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AT17N256/512/010/002/040
3020A–CNFG–04/10/03
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
DC Characteristics
V
CC = 3.3V ± 10%
Symbol
Description
AT17N256
AT17N512/
AT17N010
AT17N002/
AT17N040
Units
Min
Max
Min
Max
Min
Max
V
IH
High-level Input Voltage
2.0
V
CC
2.0
V
CC
2.0
V
CC
V
VIL
Low-level Input Voltage
0
0.8
0
0.8
0
0.8
V
V
OH
High-level Output Voltage
(I
OH = -2.5 mA)
Commercial
2.4
2.4
2.4
V
V
OL
Low-level Output Voltage
(I
OL = +3 mA)
0.4
0.4
0.4
V
VOH
High-level Output Voltage
(IOH = -2 mA)
Industrial
2.4
2.4
2.4
V
V
OL
Low-level Output Voltage
(I
OL = +3 mA)
0.4
0.4
0.4
V
ICCA
Supply Current, Active Mode
5
5
5
mA
I
L
Input or Output Leakage Current
(V
IN = VCC or GND)
-1010-10
10
-1010
µA
I
CCS
Supply Current, Standby Mode
Commercial
50
100
150
µA
Industrial
100
100
150
µA
AC Characteristics
V
CC = 3.3V ± 10%
Symbol
Description
AT17N256
AT17N512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
Min
Max
Min
Max
Min
Max
Min
Max
T
OE
(1)
OE to Data Delay
50
55
50
55
ns
T
CE
(1)
CE to Data Delay
60
60
55
60
ns
TCAC
(1)
CLK to Data Delay
75
80
55
60
ns
T
OH
Data Hold from CE, OE, or CLK
0000
ns
T
DF
(2)
CE or OE to Data Float Delay
55
55
50
50
ns
TLC
CLK Low Time
25
25
25
25
ns
T
HC
CLK High Time
25
25
25
25
ns
T
SCE
CE Setup Time to CLK
(to guarantee proper counting)
35
60
30
35
ns
T
HCE
CE Hold Time from CLK
(to guarantee proper counting)
0000
ns
T
HOE
OE High Time (guarantees counter is reset)
25
25
25
25
ns
F
MAX
Maximum Clock Frequency
10
10
15
10
MHz


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