Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AM29F032B Datasheet(PDF) 3 Page - Advanced Micro Devices

Part No. AM29F032B
Description  32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Download  39 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29F032B Datasheet(HTML) 3 Page - Advanced Micro Devices

  AM29F032B Datasheet HTML 1Page - Advanced Micro Devices AM29F032B Datasheet HTML 2Page - Advanced Micro Devices AM29F032B Datasheet HTML 3Page - Advanced Micro Devices AM29F032B Datasheet HTML 4Page - Advanced Micro Devices AM29F032B Datasheet HTML 5Page - Advanced Micro Devices AM29F032B Datasheet HTML 6Page - Advanced Micro Devices AM29F032B Datasheet HTML 7Page - Advanced Micro Devices AM29F032B Datasheet HTML 8Page - Advanced Micro Devices AM29F032B Datasheet HTML 9Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 39 page
background image
2
Am29F032B
GENERAL DESCRIPTION
The Am29F032B is a 32 Mbit, 5.0 volt-only Flash
memory organized as 4,194,304 bytes of 8 bits each.
The 4 Mbytes of data are divided into 64 sectors of 64
Kbytes each for flexible erase capability. The 8 bits of
data appear on DQ0–DQ7. The Am29F032B is offered
in 40 -pin TSOP and 44-pin SO pa ckages. The
Am29F032B is manufactured using AMD’s 0.32 µm
process technology. This device is designed to be pro-
grammed in-system with the standard system 5.0 volt
V
CC supply. A 12.0 volt VPP is not required for program
or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
The standard device offers access times of 70, 90,
120, and 150 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus con-
tention, the device has separate chip enable (CE#),
write enable (WE#), and output enable (OE#) controls.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for
the programming and erase operations. Reading data
out of the device is similar to reading from 12.0 volt
Flash or EPROM devices.
The device is programmed by executing the program
command sequence. This invokes the Embedded Pro-
gram algorithm—an internal algorithm that automati-
cally times the program pulse widths and verifies
proper cell margin. The device is erased by executing
the erase command sequence. This invokes the Em-
bedded Erase algorithm—an internal algorithm that
automatically preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. A sector is typically
erased and verified within one second. The device is
erased when shipped from the factory.
The hardware sector group protection feature disables
both program and erase operations in any combination
of the eight sector groups of memory. A sector group
consists of four adjacent sectors.
The Erase Suspend feature enables the system to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.
True background erase can thus be achieved.
The device requires only a single 5.0 volt power supply
for both read and write functions. Internally generated
and regulated voltages are provided for the program
and erase operations. A low V
CC detector automati-
cally inhibits write operations during power transitions.
The host system can detect whether a program or
erase cycle is complete by using the RY/BY# pin, the
DQ7 (Data# Polling) or DQ6 (toggle) status bits. After
a program or erase cycle has been completed, the de-
vice automatically returns to the read mode.
A hardware RESET# pin terminates any operation in
progress. The internal state machine is reset to the
read mode. The RESET# pin may be tied to the sys-
tem reset circuitry. Therefore, if a system reset occurs
during either an Embedded Program or Embedded
Erase algorithm, the device is automatically reset to the
read mode. This enables the system’s microprocessor
to read the boot-up firmware from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t leve ls o f qu al it y, r e li ab il it y, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at
a time using the programming mechanism of hot
electron injection.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn