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ADS1112IDRCT Datasheet(PDF) 10 Page - Burr-Brown (TI) |
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ADS1112IDRCT Datasheet(HTML) 10 Page - Burr-Brown (TI) |
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10 / 18 page  ADS1112 SBAS282D − JUNE 2003 − REVISED MARCH 2004 www.ti.com 10 A0 A1 SLAVE ADDRESS 0 0 1001000 0 Float 1001001 0 1 1001010 1 0 1001100 1 Float 1001101 1 1 1001110 Float 0 1001011 Float 1 1001111 Float Float Invalid Table 4. Address Pins and Slave Address for the ADS1112. I2C DATA RATES The I2C bus operates in one of three speed modes. Standard mode allows a clock frequency of up to 100kHz; fast mode permits a clock frequency of up to 400kHz; and high-speed mode (also called Hs mode), which allows a clock frequency of up to 3.4MHz. The ADS1112 is fully compatible with all three modes. No special action needs to be taken to use the ADS1112 in standard or fast modes, but high-speed mode must be activated. To activate high-speed mode, send a special address byte of 00001xxx following the START condition, where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. (Note that this is different from normal address bytes; the low bit does not indicate read/write status.) The ADS1112 will not acknowledge this byte; the I2C specification prohibits acknowledgment of the Hs master code. On receiving a master code, the ADS1112 will switch on its Hs mode filters, and communicate at up to 3.4MHz. The ADS1112 will switch out of Hs mode with the next STOP condition. For more information on high-speed mode, consult the I2C specification. REGISTERS The ADS1112 has two registers that are accessible via its I2C port. The output register contains the result of the last conversion; the configuration register allows the user to change the ADS1112 operating mode and query the status of the device. OUTPUT REGISTER The 16-bit output register contains the result of the last conversion in binary two’s complement format. Following reset or power-up, the output register is cleared to zero, and remains zero until the first conversion is completed. The output register format is shown in Table 5. BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 5. Output Register |
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