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AD5170BRM100 Datasheet(PDF) 12 Page - Analog Devices |
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AD5170BRM100 Datasheet(HTML) 12 Page - Analog Devices |
12 / 24 page AD5170 Rev. A | Page 12 of 24 THEORY OF OPERATION SDA SCL A W B FUSES EN DAC REG. I2C INTERFACE COMPARATOR ONE-TIME PROGRAM/TEST CONTROL BLOCK MUX DECODER FUSE REG. Figure 30. Detailed Functional Block Diagram The AD5170 is a 256-position, digitally controlled variable resistor (VR) that employs fuse link technology to achieve memory retention of resistance setting. An internal power-on preset places the wiper at midscale during power-on. If the OTP function has been activated, the device powers up at the user-defined permanent setting. ONE-TIME PROGRAMMING (OTP) Prior to OTP activation, the AD5170 presets to midscale during initial power-on. After the wiper is set at the desired position, the resistance can be permanently set by programming the T bit high along with the proper coding (see Table 7 and Table 8) and one time VDD_OTP. Note that fuse link technology of the AD517x family of digital pots requires VDD_OTP between 5.25 V and 5.5 V to blow the fuses to achieve a given nonvolatile setting. On the other hand, VDD can be 2.7 V to 5.5 V during operation. As a result, system supply that is lower than 5.25 V requires external supply for one-time programming. Note that the user is allowed only one attempt in blowing the fuses. If the user fails to blow the fuses at the first attempt, the fuses’ structures may have changed such that they may never be blown regardless of the energy applied at subsequent events. For details, see the Power Supply Considerations section. The device control circuit has two validation bits, E1 and E0, that can be read back to check the programming status (see Table 7). Users should always read back the validation bits to ensure that the fuses are properly blown. After the fuses have been blown, all fuse latches are enabled upon subsequent power-on; therefore, the output corresponds to the stored setting. Figure 30 shows a detailed functional block diagram. PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of 256 possible settings. A W B A W B A W B Figure 31. Rheostat Mode Configuration Assuming a 10 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Because there is a 50 Ω wiper contact resistance, such a connection yields a minimum of 100 Ω (2 × 50 Ω) resistance between Terminal W and Terminal B. The second connection is the first tap point, which corresponds to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for data 0x01. The third connection is the next tap point, repre- senting 178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW). |
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