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74LVC1G11GV Datasheet(PDF) 1 Page - NXP Semiconductors

Part # 74LVC1G11GV
Description  Single 3-input AND gate
Download  14 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC1G11GV Datasheet(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74LVC1G11 is a high-performance, low-voltage, Si-gate CMOS device and superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
The 74LVC1G11 provides a single 3-input AND gate.
2.
Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant inputs for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V).
s
±24 mA output drive (V
CC = 3.0 V)
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Multiple package options
s Specified from
−40 °Cto+85 °C and −40 °C to +125 °C.
74LVC1G11
Single 3-input AND gate
Rev. 01 — 30 November 2004
Product data sheet


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