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56F8345 Datasheet(PDF) 8 Page - Motorola, Inc |
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56F8345 Datasheet(HTML) 8 Page - Motorola, Inc |
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8 / 148 page  8 56F8345 Technical Data Preliminary Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. 56800E Program Flash Program RAM Data RAM pab[20:0] xab1[23:0] xab2[23:0] EMI* 11 4 6 Data Flash pdb_m[15:0] cdbw[31:0] cdbr_m[31:0] xdb2_m[15:0] Address Data Control IPBus Bridge IPBus JTAG / EOnCE 5 Boot Flash Flash Memory Module To Flash Control Logic CHIP TAP Controller TAP Linking Module External JTAG Port * EMI not functional in this package; since only part of the address/data bus is bonded out, use as GPIO pins Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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