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MF10 Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. MF10
Description  Universal Monolithic Dual Switched Capacitor Filter
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

MF10 Datasheet(HTML) 2 Page - National Semiconductor (TI)

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Absolute Maximum Ratings (Note 1)
If MilitaryAerospace specified devices are required
please contact the National Semiconductor Sales
OfficeDistributors for availability and specifications
Supply Voltage (Va b Vb)
14V
Voltage at Any Pin
Va a 03V
Vb b 03V
Input Current at Any Pin (Note 2)
5 mA
Package Input Current (Note 2)
20 mA
Power Dissipation (Note 3)
500 mW
Storage Temperature
150 C
ESD Susceptability (Note 11)
2000V
Soldering Information
N Package 10 sec
260 C
J Package 10 sec
300 C
SO Package Vapor Phase (60 Sec)
215 C
Infrared (15 Sec)
220 C
See AN-450 ‘‘Surface Mounting Methods and Their Effect
on Product Reliability’’ (Appendix D) for other methods of
soldering surface mount devices
Operating Ratings (Note 1)
Temperature Range
TMIN s TA s TMAX
MF10ACN MF10CCN
0 C s TA s 70 C
MF10CCWM MF10ACWM
0 C s TA s 70 C
MF10CCJ
b
40 C s TA s 85 C
MF10AJ
b
55 C s TA s 125 C
Electrical Characteristics Va ea500V and Vb eb500V unless otherwise specified Boldface limits
apply for TMIN to TMAX all other limits TA e TJ e 25 C
MF10ACN MF10CCN
MF10CCJ MF10AJ
MF10ACWM MF10CCWM
Symbol
Parameter
Conditions
Typical
Tested
Design
Typical
Tested
Design Units
(Note 8)
Limit
Limit
(Note 8)
Limit
Limit
(Note 9) (Note 10)
(Note 9) (Note 10)
Va b Vb Supply Voltage
Min
99
V
Max
14
14
V
IS
Maximum Supply
Clock Applied to Pins 10
11
812
12
8
12
mA
Current
No Input Signal
fO
Center Frequency Min
fO c Q k 200 kHz
01
02
01
02
Hz
Range
Max
30
20
30
20
kHz
fCLK
Clock Frequency
Min
50
10
50
10
Hz
Range
Max
15
10
15
10
MHz
fCLK fO
501 Clock to
MF10A Q e 10
Vpin12 e 5V
g
02
g
06
g
06
g
02
g
10
%
Center Frequency MF10C Mode 1
fCLK e 250 kHz
g
02
g
15
g
15
g
02
g
15
%
Ratio Deviation
fCLK fO
1001 Clock to
MF10A Q e 10
Vpin12 e 0V
g
02
g
06
g
06
g
02
g
10
%
Center Frequency MF10C Mode 1
fCLK e 500 kHz
g
02
g
15
g
15
g
02
g
15
%
Ratio Deviation
Clock Feedthrough
Q e 10
10
10
mV
Mode 1
Q Error (MAX)
Q e 10
Vpin12 e 5V
g
2
g
6
g
6
g
2
g
10
%
(Note 4)
Mode 1
fCLK e 250 kHz
Vpin12 e 0V
g
2
g
6
g
6
g
2
g
10
%
fCLK e 500 kHz
HOLP
DC Lowpass Gain
Mode 1 R1 e R2 e 10k
0
g
02
g
02
0
g
02
dB
VOS1
DC Offset Voltage (Note 5)
g
50
g
20
g
20
g
50
g
20
mV
VOS2
DC Offset Voltage Min
Vpin12 ea5V SAB e Va
b
150
b
185
b
185
b
150
b
185
mV
(Note 5)
Max
(fCLK fO e 50)
b
85
b
85
b
85
Min
Vpin12 ea5V SAB e Vb
b
70
b
70
mV
Max
(fCLK fO e 50)
VOS3
DC Offset Voltage Min
Vpin12 ea5V All Modes
b
70
b
100
b
100
b
70
b
100
mV
(Note 5)
Max
(fCLK fO e 50)
b
20
b
20
b
20
VOS2
DC Offset Voltage
Vpin12 e 0V
SAB e Va
b
300
b
300
mV
(Note 5)
(fCLK fO e 100)
Vpin12 e 0V
SAB e Vb
b
140
b
140
mV
(Note 5)
(fCLK fO e 100)
VOS3
DC Offset Voltage
Vpin12 e 0V
All Modes
b
140
b
140
mV
(Note 5)
(fCLK fO e 100)
2


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