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MF10 Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. MF10
Description  Universal Monolithic Dual Switched Capacitor Filter
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

MF10 Datasheet(HTML) 6 Page - National Semiconductor (TI)

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Pin Descriptions (Continued)
LSh(9)
Level shift pin it accommodates various
clock levels with dual or single supply
operation With dual g5V supplies the
MF10 can be driven with CMOS clock
levels (g5V) and the LSh pin should be
tied to the system ground If the same
supplies as above are used but only TTL
clock levels derived from 0V to a5V
supply are available the LSh pin should
be tied to the system ground For single
supply operation (0V and a10V) the
VAb VDb pins should be connected to
the system ground
the AGND pin
should be biased at a5V and the LSh
pin should also be tied to the system
ground for TTL clock levels LSh should
be biased at a5V for CMOS clock lev-
els in 10V single-supply applications
CLKA(10)
Clock inputs for each switched capaci-
CLKB(11)
tor filter building block They should both
be of the same level (TTL or CMOS)
The level shift (LSh) pin description dis-
cusses how to accommodate their lev-
els The duty cycle of the clock should
be close to 50% especially when clock
frequencies above 200 kHz are used
This allows the maximum time for the
internal op-amps to settle which yields
optimum filter operation
50100CL(12)
By tying this pin high a 501 clock-to-fil-
ter-center-frequency ratio is obtained
Tying this pin at mid-supplies (ie analog
ground with dual supplies) allows the fil-
ter to operate at a 1001 clock-to-cen-
ter-frequency ratio When the pin is tied
low (ie negative supply with dual sup-
plies) a simple current limiting circuit is
triggered to limit the overall supply cur-
rent down to about 25 mA The filtering
action is then aborted
AGND(15)
This is the analog ground pin This pin
should be connected to the system
ground for dual supply operation or bi-
ased to mid-supply for single supply op-
eration For a further discussion of mid-
supply biasing techniques see the Appli-
cations Information (Section 32) For
optimum filter performance a ‘‘clean’’
ground must be provided
10 Definition of Terms
fCLK the frequency of the external clock signal applied to
pin 10 or 11
fO center frequency of the second order function complex
pole pair fO is measured at the bandpass outputs of the
MF10 and is the frequency of maximum bandpass gain
(Figure 1)
fnotch the frequency of minimum (ideally zero) gain at the
notch outputs
fz the center frequency of the second order complex zero
pair if any If fz is different from fO and if QZ is high it can be
observed as the frequency of a notch at the allpass output
(Figure 10)
Q
‘‘quality factor’’ of the 2nd order filter Q is measured at
the bandpass outputs of the MF10 and is equal to fO divided
by the b3 dB bandwidth of the 2nd order bandpass filter
(Figure 1) The value of Q determines the shape of the 2nd
order filter responses as shown in
Figure 6
QZ the quality factor of the second order complex zero pair
if any QZ is related to the allpass characteristic which is
written
HAP(s) e
HOAP
s2bs
0O
QZ
a
0O2
J
s2 a
s0O
Q
a
0O2
where QZ e Q for an all-pass response
HOBP the gain (in VV) of the bandpass output at f e fO
HOLP the gain (in VV) of the lowpass output as f
x 0Hz
(Figure 2)
HOHP the gain (in VV) of the highpass output as f
x
fCLK 2 (Figure 3)
HON the gain (in VV) of the notch output as f
x 0Hz
and as f
x fCLK 2 when the notch filter has equal gain
above and below the center frequency
(Figure 4) When the
low-frequency gain differs from the high-frequency gain as
in modes 2 and 3a
(Figures 11 and 8) the two quantities
below are used in place of HON
HON1 the gain (in VV) of the notch output as f
x 0 Hz
HON2 the gain (in VV) of the notch output as f
x fCLK 2
6


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