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LP3470IM5X-4.00 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # LP3470IM5X-4.00
Description  Tiny Power On Reset Circuit
Download  8 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LP3470IM5X-4.00 Datasheet(HTML) 3 Page - National Semiconductor (TI)

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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC Voltage
−0.3V to +6V
Reset Voltage
−0.3V to +6V
Output Current (Reset)
10 mA
Operating Temperature Range
LP3470
−20˚C to +85˚C
LP3470I
−40˚C to +85˚C
Junction Temperature (T
Jmax)
125˚C
Power Dissipation (T
A = 25˚C) (Note
2)
300 mW
θ
JA (Note 2)
280˚C/W
Storage Temp. Range
−65˚C to +150˚C
Lead Temp. (Soldering, 5 sec)
260˚C
ESD Rating (Note 3)
2 kV
Electrical Characteristics
Limits in standard typeface are for T
J = 25˚C, and limits in boldface type apply over the full operating temperature range, un-
less otherwise specified. V
CC = +2.4V to +5.0V unless otherwise noted.
Symbol
Parameter
Conditions
Typ
(Note
4)
Min
(Note
5)
Max
(Note
5)
Units
V
CC
Operating Voltage Range
0.5
5.5
V
I
CC
V
CC Supply Current
V
CC = 4.5V
16
30
µA
V
RTH
Reset Threshold Voltage (Note 6)
LP3470
V
RTH
0.99
V
RTH
0.99
V
RTH
1.01
V
RTH
1.01
V
RTH
V
LP3470I
V
RTH
0.99
V
RTH
0.985
V
RTH
1.01
V
RTH
1.015
V
RTH
V
HYST
Hysteresis Voltage (Note 7)
35
15
65
mV
t
PD
V
CC to Reset Delay
V
CC falling at 1 mV/µs
100
300
µs
t
RP
Reset Timeout Period (Note 8)
C
1 =1nF
2
1.0
3.5
ms
V
OL
Reset Output Voltage Low
V
CC = 0.5V; IOL =30µA
0.1
V
V
CC = 1.0V; IOL = 100 µA
0.1
V
CC =VRTH −100 mV; IOL =4mA
0.4
R
1
External Pull-up Resistor
20
0.68
68
k
I
LEAK
Reset Output Leakage Current
0.15
1
µA
6
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device
beyond its operating conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (Maximum Junction Temperature), θJA (Junction to
Ambient Thermal Resistance), and TA (Ambient Temperature). The maximum allowable power dissipation at any temperature is PDmax =(TJmax −TA)/ θJA or the
number given in the Absolute Maximum Ratings, whichever is lower.
Note 3: The Human Body Model is a 100 pF capacitor discharged through a 1.5 k
Ω resistor into each pin.
Note 4: Typical numbers are at 25˚C and represent the most likely parametric norm.
Note 5: Min. and Max. limits in standard typeface are 100% production tested at 25˚C. Min. and Max. limits in boldface are guaranteed through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 6: Factory-trimmed reset thresholds are available in 50 mV increments from 2.4V to 5.0V. Contact your National Semiconductor representative.
Note 7: VHYST affects the relation between VCC and Reset as shown in the timing diagram.
Note 8: tRP is programmable by varying the value of the external capacitor (C1) connected to pin SRT. The equation is: tRP =2000xC1 (C1 in µF and tRP in ms).
www.national.com
3


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