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XRT71D00 Datasheet(PDF) 4 Page - Exar Corporation

Part No. XRT71D00
Description  E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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XRT71D00 Datasheet(HTML) 4 Page - Exar Corporation

 
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E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER XRT71D00
REV. 1.01
4
PIN DESCRIPTIONS
PIN DESCRIPTION
PIN #NAME
TYPE
DESCRIPTION
1NC
***
This pin is not connected internally
2
RNEG
I
Receive Negative Data (Jittery)
The input jittery negative data is sampled either on the rising or falling
edge of RClk depending on the setting of ClkES (pin 10).
If ClkES is “high”, then RNEG will be sampled on the falling edge of RClk.
If ClkES is “low”, then RPOS will be sampled on the rising edge of RClk.
This pin is typically tied to the “RNEG” output pin of the LIU.
3
RClk
I
Receive Clock (Jittery)
Clock input RClk should be connected to the recovered clock.
4
GND
***
Digital Ground
5MClk
I
Master Clock Input.
Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/-
20ppm. This clock must be continuous and jitter free with duty cycle
between 30 to 70%.
NOTE: It is permissible to use the EXClk signal orSTS-1 clock.
6
GND
***
Analog Ground
7VDD
***
Analog Positive Supply: 3.3V or 5.0V ± 5%
8STS-1
I
SONET STS-1 Mode Select:
This pin along with the E3/DS3* select pin (pin 29) configures the
XRT71D00 either in E3, DS3 or STS-1 mode.
A table relating to the setting of the pins is given below:
STS-1
E3/DS3*
XRT71D00 Operating Mode
0
0
DS3 (44.736 MHz)
0
1
E3 (34.368 MHz)
1
0
STS-1 (51.84 MHz)
1
1
E3 (34.368 MHz)
NOTES:
1. This input pin is active only in the Hardware Mode
2. Internal 50 K Ohm pull-up resistor.
9NC
***
This pin is not connected internally
10
ClkES/(SDI)
I
Clock Edge Select Input/Serial Data Input Pin.
The function of this pin depends on whether XRT71D00 is configured in
Harware or Host Mode.
Hardware Mode—Clock Edge Select Input
The status of this pin determines the sampling edge on RClk to RPOS/
RNEG and RRPOS/RRNEG data update on RRClk edge.
When high:
RPOS/RNEG is sampled on falling edge of RClk and
RRPOS/RRNEG is updated on rising edge of RRClk.
When low:
RPOS/RNEG is sampled on rising edge of RClk and
RRPOS/RRNEG is updated on falling edge of RRClk.
Host Mode—Serial Data Input
The address value (of the command registers) or the data value is either
Read or Written through this pin.
The input data will be sampled on the rising edge of the SClk pin (pin 11).


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