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XA-G39 Datasheet(PDF) 33 Page - NXP Semiconductors

Part No. XA-G39
Description  XA 16-bit microcontroller family XA 16-bit microcontroller 32K FLASH/1K RAM, watchdog, 2 UARTs
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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XA-G39 Datasheet(HTML) 33 Page - NXP Semiconductors

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Philips Semiconductors
Preliminary data
XA-G39
XA 16-bit microcontroller family
32K Flash/1K RAM, watchdog, 2 UARTs
2002 Mar 13
33
AC ELECTRICAL CHARACTERISTICS (5 V)
VDD = 4.5 V to 5.5 V; Tamb = 0 to +70 °C for commercial; VDD = 4.75 V to 5.25 V, –40 °C to +85 °C for industrial.
SYMBOL
FIGURE
PARAMETER
VARIABLE CLOCK
UNIT
SYMBOL
FIGURE
PARAMETER
MIN
MAX
UNIT
External Clock
fC
Oscillator frequency
0
30
MHz
tC
26
Clock period and CPU timing cycle
1/fC
ns
tCHCX
26
Clock high time
tC * 0.5 7
ns
tCLCX
26
Clock low time
tC * 0.4 7
ns
tCLCH
26
Clock rise time
5
ns
tCHCL
26
Clock fall time
5
ns
Address Cycle
tCRAR
25
Delay from clock rising edge to ALE rising edge
5
46
ns
tLHLL
20
ALE pulse width (programmable)
(V1 * tC) – 6
ns
tAVLL
20
Address valid to ALE de-asserted (set-up)
(V1 * tC) – 14
ns
tLLAX
20
Address hold after ALE de-asserted
(tC/2) – 10
ns
Code Read Cycle
tPLPH
20
PSEN pulse width
(V2 * tC) – 10
ns
tLLPL
20
ALE de-asserted to PSEN asserted
(tC/2) – 7
ns
tAVIVA
20
Address valid to instruction valid, ALE cycle (access time)
(V3 * tC) – 36
ns
tAVIVB
21
Address valid to instruction valid, non-ALE cycle (access time)
(V4 * tC) – 29
ns
tPLIV
20
PSEN asserted to instruction valid (enable time)
(V2 * tC) – 29
ns
tPXIX
20
Instruction hold after PSEN de-asserted
0
ns
tPXIZ
20
Bus 3-State after PSEN de-asserted (disable time)
tC – 8
ns
tIXUA
20
Hold time of unlatched part of address after instruction latched
0
ns
Data Read Cycle
tRLRH
22
RD pulse width
(V7 * tC) – 10
ns
tLLRL
22
ALE de-asserted to RD asserted
(tC/2) – 7
ns
tAVDVA
22
Address valid to data input valid, ALE cycle (access time)
(V6 * tC) – 36
ns
tAVDVB
23
Address valid to data input valid, non-ALE cycle (access time)
(V5 * tC) – 29
ns
tRLDV
22
RD low to valid data in, enable time
(V7 * tC) – 29
ns
tRHDX
22
Data hold time after RD de-asserted
0
ns
tRHDZ
22
Bus 3-State after RD de-asserted (disable time)
tC – 8
ns
tDXUA
22
Hold time of unlatched part of address after data latched
0
ns
Data Write Cycle
tWLWH
24
WR pulse width
(V8 * tC) – 10
ns
tLLWL
24
ALE falling edge to WR asserted
(V12 * tC) – 10
ns
tQVWX
24
Data valid before WR asserted (data setup time)
(V13 * tC) – 22
ns
tWHQX
24
Data hold time after WR de-asserted (Note 6)
(V11 * tC) – 7
ns
tAVWL
24
Address valid to WR asserted (address setup time) (Note 5)
(V9 * tC) – 22
ns
tUAWH
24
Hold time of unlatched part of address after WR is de-asserted
(V11 * tC) – 7
ns
Wait Input
tWTH
25
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
(V10 * tC) – 30
ns
tWTL
25
WAIT hold after bus strobe (RD, WR, or PSEN) assertion
(V10 * tC) – 5
ns
NOTES:
1. Load capacitance for all outputs = 80pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL).
Refer to the
XA User Guide for details of the bus timing settings.
V1)
This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register.
V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.


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