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XA-G39 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. XA-G39
Description  XA 16-bit microcontroller family XA 16-bit microcontroller 32K FLASH/1K RAM, watchdog, 2 UARTs
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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XA-G39 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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Philips Semiconductors
Preliminary data
XA-G39
XA 16-bit microcontroller family
32K Flash/1K RAM, watchdog, 2 UARTs
2
2002 Mar 13
GENERAL DESCRIPTION
The XA-G39 is a member of Philips’ 80C51 XA (eXtended
Architecture) family of high performance 16-bit single-chip
microcontrollers.
The XA-G39 contains 32 kbytes of Flash program memory, and
provides three general purpose timers/counters, a watchdog timer,
dual UARTs, and four general purpose I/O ports with programmable
output configurations.
A default serial loader program in the Boot ROM allows In-System
Programming (ISP) of the Flash memory without the need for a
loader in the Flash code. User programs may erase and reprogram
the Flash memory at will through the use of standard routines
contained in the Boot ROM (In-Application Programming).
FEATURES
32 kbytes of on-chip Flash program memory with In-System
Programming capability
Three Flash blocks = two 8 kbyte blocks and one 16 kbyte block
Provides Flash solution for XA-G37 (OTP) designs
Single supply voltage In-System Programming (ISP) of the Flash
memory (VPP = VDD, or VPP = 12 V if desired)
Boot ROM contains low level Flash programming routines for
In-Application Programming and a default serial loader using the
UART
1024 bytes of on-chip data RAM
Supports off-chip program and data addressing up to 1 megabyte
(20 address lines)
Three standard counter/timers with enhanced features (same as
XA-G3 T0, T1, and T2). All timers have a toggle output capability
Watchdog timer
Two enhanced UARTs with independent baud rates
Seven software interrupts
Four 8-bit I/O ports, with 4 programmable output configurations for
each pin
30 MHz operating frequency at 5 V
Power saving operating modes: Idle and Power-Down.
Wake-Up from power-down via an external interrupt is supported.
44-pin PLCC package
BLOCK DIAGRAM
TIMER 2
UART 1
UART 0
XA CPU Core
WATCHDOG
TIMER
PORT 0
PORT 1
PORT 2
1024 BYTES
STATIC RAM
32 KBYTES
FLASH
SFR
bus
PORT 3
Program
Memory
Bus
Data
Bus
SU01594
TIMER 0, 1


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