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UPD72874 Datasheet(PDF) 13 Page - NEC |
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UPD72874 Datasheet(HTML) 13 Page - NEC |
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13 / 40 page  Preliminary Data Sheet S15306EJ2V0DS 13 µµµµPD72874 2. PHY REGISTERS 2.1 Complete Structure for PHY Registers Figure 2-1. Complete Structure of PHY Registers 01 23 45 6 7 0000 Physical_ID R PS 0001 RHB IBR Gap_count 0010 Extended (7) Reserved Total_ports 0011 Max_speed Reserved Delay 0100 Link_active Contender Jitter Pwr_class 0101 Watchdog ISBR Loop Pwr_fail Timeout Port_event Enab_accel Enab_multi 0110 Reserved 0111 Page_select Reserved Port_select 1000 Register0 (page_select) 1001 Register1 (page_select) 1010 Register2 (page_select) 1011 Register3 (page_select) 1100 Register4 (page_select) 1101 Register5 (page_select) 1110 Register6 (page_select) 1111 Register7 (page_select) Table 2-1. Bit Field Description (1/3) Field Size R/W Reset value Description Physical_ID 6 R 000000 Physical_ID value selected from Self_ID period. R 1 R 0 If this bit is 1, the node is root. 1: Root 0: Not root PS 1 R Cable power status. 1: Cable power on 0: Cable power off RHB 1 R/W 0 Root Hold -off bit. If 1, becomes root at the bus reset. IBR 1 R/W 0 Initiate bus reset. Setting to 1 begins a long bus reset. Long bus reset signal duration: 166 µsec. Returns to 0 at the beginning of bus reset. Gap_count 6 R/W 111111 Gap count value. It is updated by the changes of transmitting and receiving the PHY configuration packet Tx/Rx. The value is maintained after first bus reset. After the second bus reset it returns to reset value. Extended 3 R 111 Shows the extended register map. |
Similar Part No. - UPD72874 |
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Similar Description - UPD72874 |
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