TMS55165 datasheet(15/70 Pages) TI

15 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

15

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

byte-write (continued)

For late-write or read-modify-write cycles, WEL and WEU are both held high before CAS falls. After CAS falls,

either or both WEL and WEU are brought low to select the corresponding byte or bytes to be written. The data

is latched in with data setup and hold times for DQ0 – DQ15 referenced to the first falling edge of WEx

(see Figure 5).

DQ0 – DQ15

WEU

WEL

CAS

RAS

Valid Input

th(WLD)†

tsu(DWL)†

† See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.

Figure 5. Example of a Late-Write Cycle

write-per-bit

The write-per-bit function allows masking any combination of the 16 DQs on any write cycle. The write-per-bit

operation is invoked when either or both WEL and WEU are held low on the falling edge of RAS. Either WEx

allows entry of the entire 16-bit mask on DQ0 – DQ15. Byte control of the mask input is not allowed. If both WEL

and WEU are held high on the falling edge of RAS, the write operation is performed without any masking. There

are two write-per-bit modes: the nonpersistent write-per-bit and the persistent write-per-bit.

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