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ML9092-02 Datasheet(PDF) 14 Page - LAPIS Semiconductor Co., Ltd. |
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ML9092-02 Datasheet(HTML) 14 Page - LAPIS Semiconductor Co., Ltd. |
14 / 66 page FEDL9092-01 LAPIS Semiconductor ML9092-01/02/03/04 14/66 ML9092-04 Function Pin Symbol Type Description 63 CS I Chip select signal input pin 64 CP I Shift clock signal input pin. This pin is connected to the Schmitt circuit internally. 65 DI/O I/O Serial data signal I/O pin. This pin is connected to the Schmitt circuit internally. CPU interface 66 KREQ O Key scan read and rotary encoder read READY signal output pin. 74 OSC1 I Oscillation 75 OSC2 O Connect external resistors with this pin. This pin is connected to the Schmitt circuit internally. If using an external clock, input it from the OSC1 pin and leave the OSC2 pin open. 67 RESET I Reset input. Initial settings can be established by applying a “L” level to this pin. This pin is connected to the Schmitt circuit internally. Control signal 76 TEST I Test input pin. This pin is connected to the VSS pin. 62–58 C0–C4 I Input pins that detect status of key switches. These pins are connected to the Schmitt circuit internally. 57–53 R0–R4 O Key switch scan signal output pins Switch signal 51, 52 A, B I Rotary encoder signal input pins. These pins are connected to the Schmitt circuit internally. Port output 77 80–78 PA0 PB0–PB2 O Port A output pin Port B output pins 50–1, 100–91 SEG1–SEG60 O LCD segment driver output pins LCD driver output 90–81 COM1–COM10 O LCD common driver output pins 73 VDD — Logic power supply pin 68 VSS — GND pin 72 VHIN — High-voltage power supply pin 71, 69 V0, V2 — LCD bias pins Power supply 70 NC — Should be left open. |
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