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FEDL9058E-01 Datasheet(PDF) 9 Page - LAPIS Semiconductor Co., Ltd. |
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FEDL9058E-01 Datasheet(HTML) 9 Page - LAPIS Semiconductor Co., Ltd. |
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9 / 76 page  FEDL9058E-01 LAPIS Semiconductor ML9058E 9/76 [VDD = 4.5 to 5.5 V, Tj = –40 to +85°C] Rated value Parameter Symbol Condition Min Max Unit Address hold time tAH8 5 — Address setup time tAW8 5 — System cycle time tCYC8 166 — Control L pulse width ( WR) tCCLW 30 — Control L pulse width ( RD) tCCLR 70 — Control H pulse width ( WR) tCCHW 55 — Control H pulse width ( RD) tCCHR 55 — Data setup time tDS8 30 — Data hold time tDH8 10 — RD Access time tACC8 — 70 Output disable time tOH8 CL = 100 pF 5 50 ns [VDD = 3.7 to 4.5 V, Tj = –40 to +85°C] Rated value Parameter Symbol Condition Min Max Unit Address hold time tAH8 5 — Address setup time tAW8 5 — System cycle time tCYC8 300 — Control L pulse width ( WR) tCCLW 60 — Control L pulse width ( RD) tCCLR 120 — Control H pulse width ( WR) tCCHW 60 — Control H pulse width ( RD) tCCHR 60 — Data setup time tDS8 40 — Data hold time tDH8 15 — RD Access time tACC8 — 140 Output disable time tOH8 CL = 100 pF 10 100 ns Note 1: The input signal rise and fall times are specified as 15ns or less. When using the system cycle time for fast speed, the specified values are (tr + tf) (t CYC8 – tCCLW – tCCHW) or (tr + tf) (tCYC8 – tCCLR – tCCHR). Note 2: All timings are specified taking the levels of 20% and 80% of VDD as the reference. Note 3: The values of tCCLW and tCCLR are specified during the overlapping period of CS1 at “L” (CS2 = “H”) and the “L” levels of WR and RD, respectively. |
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