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SPT7760BIK Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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SPT7760BIK Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 8 page  SPT 4 3/10/97 SPT7760 GENERAL DESCRIPTION The SPT7760 is the fastest monolithic 8-bit parallel flash A/D converter available today. The nominal conversion rate is 1 GSPS and the analog bandwidth is in excess of 900 MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see block dia- gram). This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capaci- tance so that it remains constant over different input voltage Figure 1 - SPT7760 Typical Interface Circuit and frequency ranges and therefore makes the part easier to drive than previous flash converters. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to "trip" into or out of the active state. This gain reduces metastable states that can cause errors at the output. The SPT7760 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50 Ω loads. 50 Ω VIN VIN VRTF VRTS * U1 + - 22 Ω * U1 22 Ω -5.2 V 2N2907 VRBS VRBF 50 Ω VIN -2.0 V Reference Convert 50 Ω -2 V Pulldown (Analog) CLK NCLK VRM R R FB = Ferrite bead U1 = OP291 or equivalent with low offset/noise. R = 1 k Ω; 0.1% matched. = AGND = DGND U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver. U3 = MC10EL16 OR MC100EL16. * = 10 µF Tantalum Capacitor and 0.1 µF Chip Capacitor ** = Care must be taken to avoid exceeding the maximum rating for the input, especially during power up sequencing of the analog input driver. -5.2 V * D8B (OVR) D7B (MSB) D6B D5B D4B D3B D2B D1B D0B (LSB) D8A (OVR) D7A (MSB) D6A D5A D4A D3A D2A D1A D0A (LSB) -2.0 V Pulldown (Digital) .1 µF U2 U3 DRB (DATA READY) DRB (DATA READY) DRA (DATA READY) DRA (DATA READY) -2.0 V Pulldown (Digital) DRB DRA DRB DRA U3 ** -5.2 V FB |
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