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DA9210-xxUK2 Datasheet(PDF) 5 Page - Dialog Semiconductor |
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DA9210-xxUK2 Datasheet(HTML) 5 Page - Dialog Semiconductor |
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5 / 92 page  DA9210 DA9210 Multi-Phase 12 A DC-DC Buck Converter Datasheet Revision 2.1 28-Oct-2016 CFR0011-120-00 5 of 92 © 2016 Dialog Semiconductor Figures Figure 1: System Diagram..................................................................................................................... 2 Figure 2: Connection Diagram (48 WLCSP) ......................................................................................... 9 Figure 3: Connection Diagram (42 VFBGA) ........................................................................................ 11 Figure 4: 2-WIRE Interface Timing ...................................................................................................... 18 Figure 5: 4-WIRE Bus Timing.............................................................................................................. 20 Figure 6: Efficiency vs Output Current VOUT = 1.0 V ........................................................................... 22 Figure 7: Efficiency vs Output Current VOUT = 1.2 V ........................................................................... 22 Figure 8: Efficiency vs Output Current VOUT = 0.9 V ........................................................................... 23 Figure 9: Efficiency vs Output Current VOUT = 1.0 V, Dual Parallel Mode (24 A max) ........................ 23 Figure 10: Efficiency vs Output Current VOUT = 1.2 V, Dual Parallel Mode (24 A max) ...................... 24 Figure 11: Efficiency vs Output Current VOUT = 0.9 V, Dual Parallel Mode (24 A max) ...................... 24 Figure 12: Efficiency vs Input Voltage IOUT = 2 A ................................................................................ 25 Figure 13: Efficiency vs Input Voltage IOUT = 10 A .............................................................................. 25 Figure 14: Start-up No Load, STARTUP_CTRL = 000 (slowest), VDD = 3.6 V, VOUT = 1.0 V ............. 26 Figure 15: Start-up No Load, STARTUP_CTRL = 100, VDD = 3.6 V, VOUT = 1.0 V ............................. 26 Figure 16: Start-up No Load, STARTUP_CTRL = 111 (fastest), VDD = 3.6 V, VOUT = 1.0 V............... 27 Figure 17: Start-up 1 A Load, STARTUP_CTRL = 000 (slowest), VDD = 3.6 V, VOUT = 1.0 V............. 27 Figure 18: Start-up 1 A Load, STARTUP_CTRL = 100, VDD = 3.6 V, VOUT = 1.0 V ............................ 28 Figure 19: Start-up 1 A Load, STARTUP_CTRL = 111 (fastest), VDD = 3.6 V, VOUT = 1.0 V .............. 28 Figure 20: Start-up from EN_CHIP, no Load, STARTUP_CTRL = 100, VDD = 3.6 V, VOUT = 1.0 V.... 29 Figure 21: Switching Waveforms, PWM, no Load, VDD = 3.6 V, VOUT = 1.0 V .................................... 29 Figure 22: Voltage and Current Ripple, PWM, no Load, VDD = 3.6 V, VOUT = 1.0 V ........................... 30 Figure 23: Transient Load, PWM, Dual Mode, 8-phases 5 A to 17 A (12 A/µs), VDD = 3.7 V, VOUT = 1.0 V......................................................................................................................................... 30 Figure 24: Transient Load, PWM, Dual Mode, 8-phases 5 to17 A in 12 A/µs, VDD = 3.7 V, VOUT = 1.0 V .................................................................................................................................................... 31 Figure 25: Transient Load, Auto, Dual Mode, 8-phases 1 to 10 A in 12 A/µs, VDD = 3.7 V, VOUT = 1.0 V .................................................................................................................................................... 31 Figure 26: Transient Load, Auto, 4-phases 1 to 5 A in 10 A/µs, VDD = 3.7 V, VOUT = 1.0 V ................ 32 Figure 27: Transient Load, Auto, Dual Mode, 8-phases, 0.22 µH 1 to 10 A in 12 A/µs, VDD = 3.7 V, VOUT = 1.0 V......................................................................................................................................... 32 Figure 28: Control Ports and Interface ................................................................................................ 34 Figure 29: Concept of Control of DA9210’s Buck Output Voltage ...................................................... 37 Figure 30: Configuration of OC_PG Pin Functionality......................................................................... 42 Figure 31: OC_PG Timing Diagram (CONFIG_A = 0x16) .................................................................. 43 Figure 32: Dual Parallel Mode Configuration ...................................................................................... 45 Figure 33: GPIO Principal Block Diagram with nIRQ Signal (Example Paths) ................................... 47 Figure 34: 4-WIRE Interface................................................................................................................ 48 Figure 35: 4- WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) ............. 50 Figure 36: 4- WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘1’) ............. 50 Figure 37: 4- WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) ............. 51 Figure 38: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) ............. 51 Figure 39: Timing of the START and STOP Conditions...................................................................... 54 Figure 40: Byte Write Operation .......................................................................................................... 54 Figure 41: Examples of Byte Read Operations ................................................................................... 54 Figure 42: 2-WIRE Page Read............................................................................................................ 55 Figure 43: 2-WIRE Page Write ............................................................................................................ 55 Figure 44: 2-WIRE Repeated Write..................................................................................................... 55 Figure 45: DVC Control Interface ........................................................................................................ 57 Figure 46: Register Map ...................................................................................................................... 61 Figure 47: Package Outline Drawing (48 WLCSP) ............................................................................. 84 Figure 48: Package Outline Drawing (42 VF-BGA)............................................................................. 86 Figure 49: Line Regulation .................................................................................................................. 90 |
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