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DA9063 Datasheet(PDF) 84 Page - Dialog Semiconductor |
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DA9063 Datasheet(HTML) 84 Page - Dialog Semiconductor |
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84 / 219 page  DA9063 System PMIC for Mobile Application Processors Datasheet DA9063_2v1 23-Mar-2017 CFR0011-120-00 84 of 219 © 2017 Dialog Semiconductor 6.8 Control Interfaces The DA9063 is register controlled by the host software. The DA9063 offers two independent serial control interfaces to access these registers (Figure 20). The communication via the main power manager interface is selected via control IF_TYPE during the initial OTP read to be either a 2- or 4- WIRE connection (I 2C respective SPI compliant). The alternate interface is a fixed 2-WIRE bus. Data is shifted into or out from DA9063 under the control of the host processor that also provides the serial clock. The interfaces are usually only configured once from OTP values, which are loaded during the initial start-up. The interface configuration can be changed by the host. However, care must be taken that changes are not made while the interface is active. If enabled, IF_RESET forces a reset of all control interfaces when port nSHUTDOWN is asserted. 6.8.1 Power Manager Interface (4- and 2-WIRE Control Bus) This is the dedicated power control interface from the primary host processor. In 4-WIRE mode, the interface uses a chip-select line (nCS/nSS), a clock line (SK), a data input (SI), and a data output line (SO). 6.8.1.1 4-WIRE Communication In 4-WIRE mode, the DA9063 register map is split into four pages with each page containing up to 128 registers. The register at address zero on each page is used as a page control register. The default active page after reset includes registers 0x01 to 0x7F. Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting control REVERT. Unless REVERT was asserted after modifying the active page it is recommended to read back the page control register to ensure that future data exchange accesses the intended registers. The 4-WIRE interface features a half-duplex operation (data can be transmitted and received within a single 16-bit frame) with an enhanced clock speed (up to 14 MHz). It operates at the provided host clock frequencies. Figure 20: Schematic of 4- and 2-WIRE Power Manager Bus A transmission begins when initiated by the host. Reading and writing is accomplished using an 8-bit command, which is sent by the host prior to the exchanged 8-bit data. The byte from the host begins shifting in on the SI pin under the control of the serial clock SK provided from the host. The first 7 bits specify the register address (0x01 to 0x7F) to be written or read by the host. The register address is automatically decoded after receiving the seventh address bit. The command word ends with a R/W bit which, together with the control bit R/W_POL, specifies the direction of the next data exchange. During register writing, the host continues sending out data during the following 8 SK clocks. For reading, the host stops transmitting and the 8-bit register is clocked out of the DA9063 during the consecutive 8 SK clocks of the frame. Address and data are transmitted MSB first. The polarity (active state) of nCS is defined by control bit nCS_POL. nCS resets the interface when inactive and it must be released between successive cycles. The SO output from DA9063 is normally in a high-impedance state and active only during the second half of read cycles. A pull-up or pull-down resistor may be needed on the SO line if a floating logic signal can cause unintended current consumption inside other circuits. PMIC (slave) Host processor SK SO SI nCS/nSS nCS/nSS SI SK SO nCS/nSS VDDIO VDDIO VDDIO Slave device SI SK SO nCS/nSS VDDIO 4-WIRE interface Host processor PMIC Peripheral device SI SK Peripheral device SDA SCL SCL SDA VDDIO VDDIO 2-WIRE interface |
Similar Part No. - DA9063_17 |
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Similar Description - DA9063_17 |
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