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LP339M Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # LP339M
Description  Ultra-Low Power Quad Comparator
Download  11 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LP339M Datasheet(HTML) 2 Page - National Semiconductor (TI)

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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
36 V
DC or ±18 VDC
Differential Input Voltage
±36 V
DC
Input Voltage
−0.3 V
DC to 36 VDC
Power Dissipation (Note 2)
Molded DIP
570 mW
Output Short Circuit to GND (Note 3)
Continuous
Input Current V
IN<−0.3 VDC (Note 4)
50 mA
Operating Temperature Range
0˚C to +70˚C
Storage Temperature Range
−65˚ to +150˚C
Soldering Information:
Dual-In-Line Package (10 sec.)
+260˚C
S.O. Package:
Vapor Phase (60 sec.)
+215˚C
Infrared (15 sec.)
+220˚C
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
Electrical Characteristics
(V+=5V
DC) (Note 5)
Parameter
Conditions
Min
Typ
Max
Units
Input Offset Voltage
T
A=25˚C (Note 10)
±2
±5mV
DC
Input Bias Current
I
IN(+) or IIN(−) with the
2.5
25
nA
DC
Output in the Linear Range, T
A=25˚C (Note 6)
Input Offset Current
I
IN(+)−IIN(−), TA=25˚C
±0.5
±5nA
DC
Input Common
T
A=25˚C (Note 7)
0
V+−1.5
V
DC
Mode Voltage Range
Supply Current
R
L=Infinite on all Comparators, TA=25˚C
60
100
µA
DC
Voltage Gain
V
O = 1VDC to 11 VDC,
500
V/mV
R
L=15 kΩ,V
+=15 V
DC,TA=25˚C
Large Signal
V
IN=TTL Logic Swing, VREF=1.4 VDC,
1.3
µSec
Response Time
V
RL=5VDC,RL=5.1 kΩ,TA=25˚C
Response Time
V
RL=5VDC,RL=5.1 kΩ,TA=25˚C (Note 8)
8
µSec
Output Sink Current
V
IN(−)=1VDC,VIN(+)=0, VO=2VDC,15
30
mA
DC
T
A=25˚C (Note 12)
V
O=0.4 VDC
0.20
0.70
mA
DC
Output Leakage Current
V
IN(+)=1VDC,VIN(−)=0, VO=5VDC,TA=25˚C
0.1
nA
DC
Input Offset Voltage
(Note 10)
±9mV
DC
Input Offset Current
I
IN(+)−IIN(−)
±1
±15
nA
DC
Input Bias Current
I
IN(+) or IIN(−) with Output in Linear Range
4
40
nA
DC
Input Common
Single Supply
0
V+−2.0
V
DC
Mode Voltage Range
Output Sink Current
V
IN(−)=1VDC,VIN(+)=0, VO=2VDC
10
mA
DC
Output Leakage Current
V
IN(+)=1VDC,VIN(−)=0, VO=30 VDC
1.0
µA
DC
Differential Input Voltage
All V
IN’s≥0VDC (or V
on split supplies) (Note 9)
36
V
DC
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits.
Note 2: For elevated temperature operation, Tj max is 125˚C for the LP339. θja (junction to ambient) is 175˚C/W for the LP339N and 120˚C/W for the LP339M when
either device is soldered in a printed circuit board in a still air environment. The low bias dissipation and the “ON-OFF” characteristic of the outputs keeps the chip
dissipation very small (PD ≤ 100 mW), provided the output transistors are allowed to saturate.
Note 3: Short circuits from the output to V+ can cause excessive heating and eventual destruction. The maximum output current is approximately 50 mA.
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP tran-
sistors becoming forward biased and thereby acting as input clamp diodes. In addition to this diode action, there is also lateral NPN parasitic transistor action on the
IC chip. This transistor action can cause the output voltage of the comparators to go to the V+ voltage level (or to ground for a large input overdrive) for the time du-
ration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which is negative, again returns to a
value greater than −0.3 VDC (TA=25˚C).
Note 5: These specifications apply for V+=5VDC and 0˚C≤TA≤70˚ C, unless otherwise stated. The temperature extremes are guaranteed but not 100% production
tested. These parameters are not used to calculate outgoing AQL.
Note 6: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output, so
no loading change exists on the reference or the input lines as long as the common-mode range is not exceeded.
Note 7: The input common-mode voltage or either input voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode volt-
age range is V+−1.5V (TA=25˚C), but either or both inputs can go to 30 VDC without damage.
Note 8: The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 1.3 µs can be obtained. See Typical Performance
Characteristics section.
www.national.com
2


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