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PCA9543 Datasheet(PDF) 7 Page - NXP Semiconductors |
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PCA9543 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 15 page Philips Semiconductors Product data sheet PCA9543 2-channel I2C switch with interrupt logic and reset 2004 Oct 01 7 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER SCL FROM MASTER SW00368 DATA OUTPUT BY RECEIVER 12 89 S START condition clock pulse for acknowledgement acknowledge not acknowledge Figure 9. Acknowledgement on the I2C-bus SDA S0 A A 11 1 0 0 A1 A0 SLAVE ADDRESS start condition R/W acknowledge from slave acknowledge from slave B0 CONTROL REGISTER XP SW00807 B1 XX XX X Figure 10. WRITE Control Register SDA S1 A NA 1 1 1 0 0 A1 A0 start condition R/W acknowledge from slave CONTROL REGISTER P stop condition last byte SW00808 SLAVE ADDRESS no acknowledge from master B0 INT0 B1 INT1 X XX X Figure 11. READ Control Register |
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