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YMF721 Datasheet(PDF) 20 Page - LSI Computer Systems |
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YMF721 Datasheet(HTML) 20 Page - LSI Computer Systems |
20 / 41 page YMF721 July 10, 1997 - 20 - 6-6. Wavetable synthesizer register 6-6-1. Status register Status Register (RO): port D7D6D5D4D3D2D1D0 OPL_Base + 4 ------ LD BUSY1 6-6-2. Data register Data Register (R/W): Index D7 D6 D5 D4 D3 D2 D1 D0 00 - 01h LSI TEST 02h DEVICE ID (“0” “1” “0”) TONE HEADER MTYPE MODE 03h Memory Address (MA21-16) 04h Memory Address (MA15-8) 05h Memory Address(MA7-0) 06h Memory Data(MD7-0) 08-1Fh TONE NUMBER (L) 20-37h F-NUMBER (L) TNUM (H) 38-4Fh BLOCK PREV F-NUMBER (H) 50-67h TOTAL LEVEL LDIR 68-7Fh KEYON DAMP LFORST CH PAN POT 80-97h CHORUS SEND LFO VIB 98-AFh AR D1R B0-C7h DL D2R C8-DFh RATE INTERPOLATION RR E0-F7h REVERB SEND - - AM F8h - - MIX CONTROL (FM-R) MIX CONTROL (FM-L) F9h - - MIX CONTROL (Wave-R) MIX CONTROL (Wave-L) FAh --- -- -- ATC FBh --- -- --- Default : After initial clear, index 02h becomes 40h (Device ID) and index F8h becomes 2Dh (-15dB), and all the other registers are cleared to "0". For the details of these registers, refer to data sheet for YMF295(OPL4-D). Note : BUSY1 is a BUSY flag for Wavetable registers. Wavetable status/Data register is normally accessed by the internal processor. |
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