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IS31LT3918-GRLS2 Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS31LT3918-GRLS2 Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
2 / 11 page IS31LT3918 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2011 2 PIN CONFIGURATION Package Pin Configurations SOP-8 PIN DESCRIPTION Pin Name Pin Number Description DIM1 1 These two pins configure the dimming levels as follows: DIM1=“floating”DIM2=“floating”, no dimming (100% only); DIM1=“floating”DIM2=“GND” , 100%-30%-100% DIM1=“GND”DIM2=“floating”, 100%-50%-100% DIM1=“GND”DIM2=“GND”, 100%-50%-20%-100% DIM2 2 ADJ 3 Linear and PWM dimming input pin. Linear dimming range: 0.5V to 2.5V. If VADJ < 0.5V, GATE output is off. If 0.5V ≤ VADJ ≤ 2.5V, VCSTH = VADJ/10. If VADJ > 2.5V, VCSTH = 0.25V. When this pin is floating, there is an internal pull up to 4.5V (typical) and VCSTH = 0.25V. PWM dimming frequency range: 200Hz -1kHz. GND 4 Ground pin. All internal currents return through this pin. GATE 5 This pin connects to the external NMOS’s gate CS 6 Current detect pin, uses an external resistor to sense the peak inductor current. Toff 7 This pin sets the off time for the switch by connecting a resistor between this pin and GND. Vin 8 8V – 450V supply voltage is connected to this pin via an external resistor. It is internally clamped and must be bypassed using a capacitor to GND. ORDERING INFORMATION INDUSTRIAL RANGE: -40°C TO +85°C Order Part No. Package QTY/Reel IS31LT3918–GRLS2-TR SOP-8, Lead-free 2500 |
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